1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2873e3ef9STom Warren /* 3873e3ef9STom Warren * (C) Copyright 2013-2015 4873e3ef9STom Warren * NVIDIA Corporation <www.nvidia.com> 5873e3ef9STom Warren */ 6873e3ef9STom Warren 7873e3ef9STom Warren #ifndef _TEGRA210_COMMON_H_ 8873e3ef9STom Warren #define _TEGRA210_COMMON_H_ 9873e3ef9STom Warren 10873e3ef9STom Warren #include "tegra-common.h" 11873e3ef9STom Warren 12873e3ef9STom Warren /* 13873e3ef9STom Warren * NS16550 Configuration 14873e3ef9STom Warren */ 15873e3ef9STom Warren #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 16873e3ef9STom Warren 17873e3ef9STom Warren /* Generic Interrupt Controller */ 18873e3ef9STom Warren #define CONFIG_GICV2 19873e3ef9STom Warren 20873e3ef9STom Warren /* 21873e3ef9STom Warren * Memory layout for where various images get loaded by boot scripts: 22873e3ef9STom Warren * 23873e3ef9STom Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 24873e3ef9STom Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 25873e3ef9STom Warren * 26873e3ef9STom Warren * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 27873e3ef9STom Warren * something else. Put it above BOOTMAPSZ to eliminate conflicts. 28873e3ef9STom Warren * 29873e3ef9STom Warren * kernel_addr_r must be within the first 128M of RAM in order for the 30873e3ef9STom Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 31873e3ef9STom Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 32873e3ef9STom Warren * should not overlap that area, or the kernel will have to copy itself 33873e3ef9STom Warren * somewhere else before decompression. Similarly, the address of any other 34873e3ef9STom Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 35873e3ef9STom Warren * this up to 16M allows for a sizable kernel to be decompressed below the 36873e3ef9STom Warren * compressed load address. 37873e3ef9STom Warren * 38873e3ef9STom Warren * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 39873e3ef9STom Warren * the compressed kernel to be up to 16M too. 40873e3ef9STom Warren * 41873e3ef9STom Warren * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 42873e3ef9STom Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 43873e3ef9STom Warren */ 44a8903167SStephen Warren #define CONFIG_LOADADDR 0x80080000 45873e3ef9STom Warren #define MEM_LAYOUT_ENV_SETTINGS \ 46873e3ef9STom Warren "scriptaddr=0x90000000\0" \ 47873e3ef9STom Warren "pxefile_addr_r=0x90100000\0" \ 48873e3ef9STom Warren "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 49873e3ef9STom Warren "fdt_addr_r=0x82000000\0" \ 50873e3ef9STom Warren "ramdisk_addr_r=0x82100000\0" 51873e3ef9STom Warren 52873e3ef9STom Warren /* For USB EHCI controller */ 53873e3ef9STom Warren #define CONFIG_EHCI_IS_TDI 54873e3ef9STom Warren #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 55873e3ef9STom Warren 56871d78edSAlexandre Courbot /* GPU needs setup */ 57871d78edSAlexandre Courbot #define CONFIG_TEGRA_GPU 58871d78edSAlexandre Courbot 59873e3ef9STom Warren #endif /* _TEGRA210_COMMON_H_ */ 60