183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 200a2749dSAllen Martin /* 300a2749dSAllen Martin * (C) Copyright 2010-2012 400a2749dSAllen Martin * NVIDIA Corporation <www.nvidia.com> 500a2749dSAllen Martin */ 600a2749dSAllen Martin 7f01b631fSTom Warren #ifndef _TEGRA20_COMMON_H_ 8f01b631fSTom Warren #define _TEGRA20_COMMON_H_ 9f01b631fSTom Warren #include "tegra-common.h" 10f01b631fSTom Warren 11f01b631fSTom Warren /* 12f01b631fSTom Warren * NS16550 Configuration 13f01b631fSTom Warren */ 14f01b631fSTom Warren #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 1500a2749dSAllen Martin 16f01b631fSTom Warren /* 17f01b631fSTom Warren * Miscellaneous configurable options 18f01b631fSTom Warren */ 19*f16e3115SJonathan Hunter #define CONFIG_STACKBASE 0x03800000 /* 56MB */ 20f01b631fSTom Warren 21f01b631fSTom Warren /*----------------------------------------------------------------------- 22f01b631fSTom Warren * Physical Memory Map 23f01b631fSTom Warren */ 24f01b631fSTom Warren 25f01b631fSTom Warren /* 26f01b631fSTom Warren * Memory layout for where various images get loaded by boot scripts: 27f01b631fSTom Warren * 28f01b631fSTom Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 29f01b631fSTom Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 30f01b631fSTom Warren * 31f940c72eSStephen Warren * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 32f940c72eSStephen Warren * something else. Put it above BOOTMAPSZ to eliminate conflicts. 33f940c72eSStephen Warren * 34f01b631fSTom Warren * kernel_addr_r must be within the first 128M of RAM in order for the 35f01b631fSTom Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 36f01b631fSTom Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 37f01b631fSTom Warren * should not overlap that area, or the kernel will have to copy itself 38f01b631fSTom Warren * somewhere else before decompression. Similarly, the address of any other 39f01b631fSTom Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 40*f16e3115SJonathan Hunter * this up to 32M allows for a sizable kernel to be decompressed below the 41f01b631fSTom Warren * compressed load address. 42f01b631fSTom Warren * 43*f16e3115SJonathan Hunter * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for 44*f16e3115SJonathan Hunter * the compressed kernel to be up to 32M too. 45f01b631fSTom Warren * 46*f16e3115SJonathan Hunter * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows 47f01b631fSTom Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 48f01b631fSTom Warren */ 4948cfca24SStephen Warren #define CONFIG_LOADADDR 0x01000000 50f01b631fSTom Warren #define MEM_LAYOUT_ENV_SETTINGS \ 51f01b631fSTom Warren "scriptaddr=0x10000000\0" \ 52f940c72eSStephen Warren "pxefile_addr_r=0x10100000\0" \ 5348cfca24SStephen Warren "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 54*f16e3115SJonathan Hunter "fdt_addr_r=0x03000000\0" \ 55*f16e3115SJonathan Hunter "ramdisk_addr_r=0x03100000\0" 56f01b631fSTom Warren 57f01b631fSTom Warren /* Defines for SPL */ 58f01b631fSTom Warren #define CONFIG_SPL_TEXT_BASE 0x00108000 59f01b631fSTom Warren #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 60f01b631fSTom Warren #define CONFIG_SPL_STACK 0x000ffffc 61f01b631fSTom Warren 62ad16617fSSimon Glass /* Align LCD to 1MB boundary */ 63ad16617fSSimon Glass #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 64ad16617fSSimon Glass 6529f3e3f2STom Warren #ifdef CONFIG_TEGRA_LP0 6600a2749dSAllen Martin #define TEGRA_LP0_ADDR 0x1C406000 6700a2749dSAllen Martin #define TEGRA_LP0_SIZE 0x2000 6800a2749dSAllen Martin #define TEGRA_LP0_VEC \ 6951926d5eSMarek Vasut "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 7051926d5eSMarek Vasut "@" __stringify(TEGRA_LP0_ADDR) " " 7100a2749dSAllen Martin #else 7200a2749dSAllen Martin #define TEGRA_LP0_VEC 7300a2749dSAllen Martin #endif 7400a2749dSAllen Martin 7500a2749dSAllen Martin /* 7600a2749dSAllen Martin * This parameter affects a TXFILLTUNING field that controls how much data is 7700a2749dSAllen Martin * sent to the latency fifo before it is sent to the wire. Without this 7800a2749dSAllen Martin * parameter, the default (2) causes occasional Data Buffer Errors in OUT 7900a2749dSAllen Martin * packets depending on the buffer address and size. 8000a2749dSAllen Martin */ 81cba0ae6eSPeter Robinson #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 8200a2749dSAllen Martin #define CONFIG_EHCI_IS_TDI 8300a2749dSAllen Martin 840dd84084SSimon Glass #define CONFIG_SYS_NAND_SELF_INIT 85a833b950SLucas Stach #define CONFIG_SYS_NAND_ONFI_DETECTION 860dd84084SSimon Glass 87f01b631fSTom Warren #endif /* _TEGRA20_COMMON_H_ */ 88