1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 20 #include <asm/arch/cpu.h> /* get chip and board defs */ 21 #include <asm/arch/omap.h> 22 23 /* Clock Defines */ 24 #define V_OSCK 26000000 /* Clock output from T2 */ 25 #define V_SCLK (V_OSCK >> 1) 26 27 #define CONFIG_MISC_INIT_R 28 29 #define CONFIG_CMDLINE_TAG 30 #define CONFIG_SETUP_MEMORY_TAGS 31 #define CONFIG_INITRD_TAG 32 #define CONFIG_REVISION_TAG 33 34 /* 35 * Size of malloc() pool 36 */ 37 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 40 /* 41 * Hardware drivers 42 */ 43 44 /* 45 * NS16550 Configuration 46 */ 47 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 48 49 #define CONFIG_SYS_NS16550_SERIAL 50 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 51 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 52 53 /* 54 * select serial console configuration 55 */ 56 #define CONFIG_CONS_INDEX 3 57 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 58 59 /* allow to overwrite serial and ethaddr */ 60 #define CONFIG_ENV_OVERWRITE 61 62 /* commands to include */ 63 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 64 #define MTDIDS_DEFAULT "nand0=nand" 65 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 66 "1920k(u-boot),128k(u-boot-env),"\ 67 "4m(kernel),-(fs)" 68 69 #define CONFIG_SYS_I2C 70 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 71 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 72 #define CONFIG_I2C_MULTI_BUS 73 74 /* 75 * TWL4030 76 */ 77 #define CONFIG_TWL4030_LED 78 79 /* 80 * Board NAND Info. 81 */ 82 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 83 /* to access nand */ 84 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 85 /* to access nand at */ 86 /* CS0 */ 87 88 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 89 /* devices */ 90 /* Environment information */ 91 92 #define CONFIG_EXTRA_ENV_SETTINGS \ 93 "loadaddr=0x82000000\0" \ 94 "console=ttyO2,115200n8\0" \ 95 "mpurate=600\0" \ 96 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 97 "tv_mode=omapfb.mode=tv:ntsc\0" \ 98 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 99 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 100 "extra_options= \0" \ 101 "mmcdev=0\0" \ 102 "mmcroot=/dev/mmcblk0p2 rw\0" \ 103 "mmcrootfstype=ext3 rootwait\0" \ 104 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 105 "nandrootfstype=ubifs\0" \ 106 "mmcargs=setenv bootargs console=${console} " \ 107 "mpurate=${mpurate} " \ 108 "${video_mode} " \ 109 "root=${mmcroot} " \ 110 "rootfstype=${mmcrootfstype} " \ 111 "${extra_options}\0" \ 112 "nandargs=setenv bootargs console=${console} " \ 113 "mpurate=${mpurate} " \ 114 "${video_mode} " \ 115 "${network_setting} " \ 116 "root=${nandroot} " \ 117 "rootfstype=${nandrootfstype} "\ 118 "${extra_options}\0" \ 119 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 120 "bootscript=echo Running bootscript from mmc ...; " \ 121 "source ${loadaddr}\0" \ 122 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 123 "mmcboot=echo Booting from mmc ...; " \ 124 "run mmcargs; " \ 125 "bootm ${loadaddr}\0" \ 126 "nandboot=echo Booting from nand ...; " \ 127 "run nandargs; " \ 128 "nand read ${loadaddr} 280000 400000; " \ 129 "bootm ${loadaddr}\0" \ 130 131 #define CONFIG_BOOTCOMMAND \ 132 "if mmc rescan ${mmcdev}; then " \ 133 "if run loadbootscript; then " \ 134 "run bootscript; " \ 135 "else " \ 136 "if run loaduimage; then " \ 137 "run mmcboot; " \ 138 "else run nandboot; " \ 139 "fi; " \ 140 "fi; " \ 141 "else run nandboot; fi" 142 143 /* 144 * Miscellaneous configurable options 145 */ 146 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 147 148 /* turn on command-line edit/hist/auto */ 149 #define CONFIG_CMDLINE_EDITING 150 #define CONFIG_AUTO_COMPLETE 151 152 #define CONFIG_SYS_ALT_MEMTEST 1 153 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 154 /* defaults */ 155 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 156 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 157 158 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 159 /* load address */ 160 #define CONFIG_SYS_TEXT_BASE 0x80008000 161 162 /* 163 * OMAP3 has 12 GP timers, they can be driven by the system clock 164 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 165 * This rate is divided by a local divisor. 166 */ 167 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 168 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 169 170 /* 171 * Physical Memory Map 172 */ 173 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 174 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 175 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 176 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 177 178 /* 179 * FLASH and environment organization 180 */ 181 182 /* **** PISMO SUPPORT *** */ 183 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 184 #define CONFIG_SYS_FLASH_BASE NAND_BASE 185 186 /* Monitor at start of flash */ 187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 188 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 189 190 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 191 192 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 193 #define CONFIG_ENV_OFFSET 0x260000 194 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 195 196 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 197 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 198 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 199 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 200 CONFIG_SYS_INIT_RAM_SIZE - \ 201 GENERATED_GBL_DATA_SIZE) 202 203 /* 204 * USB 205 * 206 * Currently only EHCI is enabled, the MUSB OTG controller 207 * is not enabled. 208 */ 209 210 /* USB EHCI */ 211 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 212 213 /* Defines for SPL */ 214 #define CONFIG_SPL_FRAMEWORK 215 216 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 217 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 218 219 #define CONFIG_SPL_NAND_BASE 220 #define CONFIG_SPL_NAND_DRIVERS 221 #define CONFIG_SPL_NAND_ECC 222 223 /* NAND boot config */ 224 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 225 #define CONFIG_SYS_NAND_PAGE_COUNT 64 226 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 227 #define CONFIG_SYS_NAND_OOBSIZE 64 228 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 229 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 230 /* 231 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 232 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 233 */ 234 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 235 10, 11, 12, 13 } 236 #define CONFIG_SYS_NAND_ECCSIZE 512 237 #define CONFIG_SYS_NAND_ECCBYTES 3 238 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 239 240 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 241 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 242 243 #define CONFIG_SPL_TEXT_BASE 0x40200800 244 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 245 CONFIG_SPL_TEXT_BASE) 246 247 /* 248 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 249 * older x-loader implementations. And move the BSS area so that it 250 * doesn't overlap with TEXT_BASE. 251 */ 252 #define CONFIG_SYS_TEXT_BASE 0x80008000 253 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 254 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 255 256 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 257 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 258 259 #endif /* __CONFIG_H */ 260