1 /* 2 * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * 4 * (C) Copyright 2007-2011 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * Configuration settings for the Allwinner sunxi series of boards. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef _SUNXI_COMMON_CONFIG_H 14 #define _SUNXI_COMMON_CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_SUNXI /* sunxi family */ 20 #ifdef CONFIG_SPL_BUILD 21 #ifndef CONFIG_SPL_FEL 22 #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ 23 #endif 24 #endif 25 26 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 28 #define CONFIG_SYS_TEXT_BASE 0x4a000000 29 30 /* 31 * Display CPU information 32 */ 33 #define CONFIG_DISPLAY_CPUINFO 34 35 /* Serial & console */ 36 #define CONFIG_SYS_NS16550 37 #define CONFIG_SYS_NS16550_SERIAL 38 /* ns16550 reg in the low bits of cpu reg */ 39 #define CONFIG_SYS_NS16550_REG_SIZE -4 40 #define CONFIG_SYS_NS16550_CLK 24000000 41 #define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE 42 #define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE 43 #define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE 44 #define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE 45 #define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE 46 47 /* DRAM Base */ 48 #define CONFIG_SYS_SDRAM_BASE 0x40000000 49 #define CONFIG_SYS_INIT_RAM_ADDR 0x0 50 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ 51 52 #define CONFIG_SYS_INIT_SP_OFFSET \ 53 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 54 #define CONFIG_SYS_INIT_SP_ADDR \ 55 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 56 57 #define CONFIG_NR_DRAM_BANKS 1 58 #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE 59 #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ 60 61 #ifdef CONFIG_AHCI 62 #define CONFIG_LIBATA 63 #define CONFIG_SCSI_AHCI 64 #define CONFIG_SCSI_AHCI_PLAT 65 #define CONFIG_SUNXI_AHCI 66 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 67 #define CONFIG_SYS_SCSI_MAX_LUN 1 68 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 69 CONFIG_SYS_SCSI_MAX_LUN) 70 #define CONFIG_CMD_SCSI 71 #endif 72 73 #define CONFIG_CMD_MEMORY 74 #define CONFIG_CMD_SETEXPR 75 76 #define CONFIG_SETUP_MEMORY_TAGS 77 #define CONFIG_CMDLINE_TAG 78 #define CONFIG_INITRD_TAG 79 80 /* mmc config */ 81 #if !defined(CONFIG_UART0_PORT_F) 82 #define CONFIG_MMC 83 #define CONFIG_GENERIC_MMC 84 #define CONFIG_CMD_MMC 85 #define CONFIG_MMC_SUNXI 86 #define CONFIG_MMC_SUNXI_SLOT 0 87 #define CONFIG_ENV_IS_IN_MMC 88 #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ 89 #endif 90 91 /* 4MB of malloc() pool */ 92 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) 93 94 /* 95 * Miscellaneous configurable options 96 */ 97 #define CONFIG_CMD_ECHO 98 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 99 #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 100 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 101 #define CONFIG_SYS_GENERIC_BOARD 102 103 /* Boot Argument Buffer Size */ 104 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 105 106 #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ 107 108 /* standalone support */ 109 #define CONFIG_STANDALONE_LOAD_ADDR 0x42000000 110 111 /* baudrate */ 112 #define CONFIG_BAUDRATE 115200 113 114 /* The stack sizes are set up in start.S using the settings below */ 115 #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ 116 117 /* FLASH and environment organization */ 118 119 #define CONFIG_SYS_NO_FLASH 120 121 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ 122 #define CONFIG_IDENT_STRING " Allwinner Technology" 123 124 #define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ 125 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 126 127 #include <config_cmd_default.h> 128 #undef CONFIG_CMD_FPGA 129 130 #define CONFIG_FAT_WRITE /* enable write access */ 131 132 #define CONFIG_SPL_FRAMEWORK 133 #define CONFIG_SPL_LIBCOMMON_SUPPORT 134 #define CONFIG_SPL_SERIAL_SUPPORT 135 #define CONFIG_SPL_LIBGENERIC_SUPPORT 136 137 #ifdef CONFIG_SPL_FEL 138 139 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" 140 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" 141 #define CONFIG_SPL_TEXT_BASE 0x2000 142 #define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ 143 144 #else /* CONFIG_SPL */ 145 146 #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 147 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ 148 149 #define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ 150 #define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ 151 152 #define CONFIG_SPL_LIBDISK_SUPPORT 153 #define CONFIG_SPL_MMC_SUPPORT 154 155 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" 156 157 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ 158 #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ 159 160 #endif /* CONFIG_SPL */ 161 162 /* end of 32 KiB in sram */ 163 #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ 164 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 165 #define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 166 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ 167 168 /* I2C */ 169 #define CONFIG_SPL_I2C_SUPPORT 170 #define CONFIG_SYS_I2C 171 #define CONFIG_SYS_I2C_MVTWSI 172 #define CONFIG_SYS_I2C_SPEED 400000 173 #define CONFIG_SYS_I2C_SLAVE 0x7f 174 #define CONFIG_CMD_I2C 175 176 /* PMU */ 177 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER 178 #define CONFIG_SPL_POWER_SUPPORT 179 #endif 180 181 #ifndef CONFIG_CONS_INDEX 182 #define CONFIG_CONS_INDEX 1 /* UART0 */ 183 #endif 184 185 /* GPIO */ 186 #define CONFIG_SUNXI_GPIO 187 #define CONFIG_SPL_GPIO_SUPPORT 188 #define CONFIG_CMD_GPIO 189 190 /* Ethernet support */ 191 #ifdef CONFIG_SUNXI_EMAC 192 #define CONFIG_MII /* MII PHY management */ 193 #endif 194 195 #ifdef CONFIG_SUNXI_GMAC 196 #define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ 197 #define CONFIG_DW_AUTONEG 198 #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ 199 #define CONFIG_PHY_ADDR 1 200 #define CONFIG_MII /* MII PHY management */ 201 #define CONFIG_PHYLIB 202 #endif 203 204 #ifdef CONFIG_USB_EHCI 205 #define CONFIG_CMD_USB 206 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 207 #define CONFIG_USB_STORAGE 208 #endif 209 210 #if !defined CONFIG_ENV_IS_IN_MMC && \ 211 !defined CONFIG_ENV_IS_IN_NAND && \ 212 !defined CONFIG_ENV_IS_IN_FAT && \ 213 !defined CONFIG_ENV_IS_IN_SPI_FLASH 214 #define CONFIG_ENV_IS_NOWHERE 215 #endif 216 217 #define CONFIG_MISC_INIT_R 218 219 #ifndef CONFIG_SPL_BUILD 220 #include <config_distro_defaults.h> 221 222 /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, 223 * 1M script, 1M pxe and the ramdisk at the end */ 224 #define MEM_LAYOUT_ENV_SETTINGS \ 225 "bootm_size=0x10000000\0" \ 226 "kernel_addr_r=0x42000000\0" \ 227 "fdt_addr_r=0x43000000\0" \ 228 "scriptaddr=0x43100000\0" \ 229 "pxefile_addr_r=0x43200000\0" \ 230 "ramdisk_addr_r=0x43300000\0" 231 232 #ifdef CONFIG_MMC 233 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 234 #else 235 #define BOOT_TARGET_DEVICES_MMC(func) 236 #endif 237 238 #ifdef CONFIG_AHCI 239 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) 240 #else 241 #define BOOT_TARGET_DEVICES_SCSI(func) 242 #endif 243 244 #ifdef CONFIG_USB_EHCI 245 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) 246 #else 247 #define BOOT_TARGET_DEVICES_USB(func) 248 #endif 249 250 #define BOOT_TARGET_DEVICES(func) \ 251 BOOT_TARGET_DEVICES_MMC(func) \ 252 BOOT_TARGET_DEVICES_SCSI(func) \ 253 BOOT_TARGET_DEVICES_USB(func) \ 254 func(PXE, pxe, na) \ 255 func(DHCP, dhcp, na) 256 257 #include <config_distro_bootcmd.h> 258 259 #define CONFIG_EXTRA_ENV_SETTINGS \ 260 MEM_LAYOUT_ENV_SETTINGS \ 261 "fdtfile=" CONFIG_FDTFILE "\0" \ 262 "console=ttyS0,115200\0" \ 263 BOOTENV 264 265 #else /* ifndef CONFIG_SPL_BUILD */ 266 #define CONFIG_EXTRA_ENV_SETTINGS 267 #endif 268 269 #endif /* _SUNXI_COMMON_CONFIG_H */ 270