1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 8 9 #define CONFIG_SYS_GENERIC_BOARD 10 11 /* Virtual target or real hardware */ 12 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 13 14 #define CONFIG_SYS_THUMB_BUILD 15 16 /* 17 * High level configuration 18 */ 19 #define CONFIG_DISPLAY_CPUINFO 20 #define CONFIG_DISPLAY_BOARDINFO_LATE 21 #define CONFIG_ARCH_EARLY_INIT_R 22 #define CONFIG_SYS_NO_FLASH 23 #define CONFIG_CLOCKS 24 25 #define CONFIG_FIT 26 #define CONFIG_OF_LIBFDT 27 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * Memory configurations 33 */ 34 #define CONFIG_NR_DRAM_BANKS 1 35 #define PHYS_SDRAM_1 0x0 36 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 37 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 38 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 39 40 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 41 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE) 42 #define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ 44 GENERATED_GBL_DATA_SIZE) 45 46 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 47 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 48 #define CONFIG_SYS_TEXT_BASE 0x08000040 49 #else 50 #define CONFIG_SYS_TEXT_BASE 0x01000040 51 #endif 52 53 /* 54 * U-Boot general configurations 55 */ 56 #define CONFIG_SYS_LONGHELP 57 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 58 #define CONFIG_SYS_PBSIZE \ 59 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 60 /* Print buffer size */ 61 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 62 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 63 /* Boot argument buffer size */ 64 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 65 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 66 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 67 #define CONFIG_SYS_HUSH_PARSER 68 69 /* 70 * Cache 71 */ 72 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC 73 #define CONFIG_SYS_CACHELINE_SIZE 32 74 #define CONFIG_SYS_L2_PL310 75 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 76 77 /* 78 * EPCS/EPCQx1 Serial Flash Controller 79 */ 80 #ifdef CONFIG_ALTERA_SPI 81 #define CONFIG_CMD_SPI 82 #define CONFIG_CMD_SF 83 #define CONFIG_SF_DEFAULT_SPEED 30000000 84 #define CONFIG_SPI_FLASH 85 #define CONFIG_SPI_FLASH_STMICRO 86 #define CONFIG_SPI_FLASH_BAR 87 /* 88 * The base address is configurable in QSys, each board must specify the 89 * base address based on it's particular FPGA configuration. Please note 90 * that the address here is incremented by 0x400 from the Base address 91 * selected in QSys, since the SPI registers are at offset +0x400. 92 * #define CONFIG_SYS_SPI_BASE 0xff240400 93 */ 94 #endif 95 96 /* 97 * Ethernet on SoC (EMAC) 98 */ 99 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 100 #define CONFIG_NET_MULTI 101 #define CONFIG_DW_ALTDESCRIPTOR 102 #define CONFIG_MII 103 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 104 #define CONFIG_PHYLIB 105 #define CONFIG_PHY_GIGE 106 #endif 107 108 /* 109 * FPGA Driver 110 */ 111 #ifdef CONFIG_CMD_FPGA 112 #define CONFIG_FPGA 113 #define CONFIG_FPGA_ALTERA 114 #define CONFIG_FPGA_SOCFPGA 115 #define CONFIG_FPGA_COUNT 1 116 #endif 117 118 /* 119 * L4 OSC1 Timer 0 120 */ 121 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 122 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 123 #define CONFIG_SYS_TIMER_COUNTS_DOWN 124 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 125 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 126 #define CONFIG_SYS_TIMER_RATE 2400000 127 #else 128 #define CONFIG_SYS_TIMER_RATE 25000000 129 #endif 130 131 /* 132 * L4 Watchdog 133 */ 134 #ifdef CONFIG_HW_WATCHDOG 135 #define CONFIG_DESIGNWARE_WATCHDOG 136 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 137 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 138 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 139 #endif 140 141 /* 142 * MMC Driver 143 */ 144 #ifdef CONFIG_CMD_MMC 145 #define CONFIG_MMC 146 #define CONFIG_BOUNCE_BUFFER 147 #define CONFIG_GENERIC_MMC 148 #define CONFIG_DWMMC 149 #define CONFIG_SOCFPGA_DWMMC 150 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 151 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 152 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 153 /* FIXME */ 154 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 155 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 156 #endif 157 158 /* 159 * I2C support 160 */ 161 #define CONFIG_SYS_I2C 162 #define CONFIG_SYS_I2C_DW 163 #define CONFIG_SYS_I2C_BUS_MAX 4 164 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 165 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 166 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 167 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 168 /* Using standard mode which the speed up to 100Kb/s */ 169 #define CONFIG_SYS_I2C_SPEED 100000 170 #define CONFIG_SYS_I2C_SPEED1 100000 171 #define CONFIG_SYS_I2C_SPEED2 100000 172 #define CONFIG_SYS_I2C_SPEED3 100000 173 /* Address of device when used as slave */ 174 #define CONFIG_SYS_I2C_SLAVE 0x02 175 #define CONFIG_SYS_I2C_SLAVE1 0x02 176 #define CONFIG_SYS_I2C_SLAVE2 0x02 177 #define CONFIG_SYS_I2C_SLAVE3 0x02 178 #ifndef __ASSEMBLY__ 179 /* Clock supplied to I2C controller in unit of MHz */ 180 unsigned int cm_get_l4_sp_clk_hz(void); 181 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 182 #endif 183 #define CONFIG_CMD_I2C 184 185 /* 186 * QSPI support 187 */ 188 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ 189 #define CONFIG_CADENCE_QSPI 190 /* Enable multiple SPI NOR flash manufacturers */ 191 #define CONFIG_SPI_FLASH /* SPI flash subsystem */ 192 #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ 193 #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ 194 #define CONFIG_SPI_FLASH_MTD 195 /* QSPI reference clock */ 196 #ifndef __ASSEMBLY__ 197 unsigned int cm_get_qspi_controller_clk_hz(void); 198 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 199 #endif 200 #define CONFIG_CQSPI_DECODER 0 201 #define CONFIG_CMD_SF 202 #endif 203 204 #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ 205 #define CONFIG_DESIGNWARE_SPI 206 #define CONFIG_CMD_SPI 207 #endif 208 209 /* 210 * Serial Driver 211 */ 212 #define CONFIG_SYS_NS16550 213 #define CONFIG_SYS_NS16550_SERIAL 214 #define CONFIG_SYS_NS16550_REG_SIZE -4 215 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 216 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 217 #define CONFIG_SYS_NS16550_CLK 1000000 218 #else 219 #define CONFIG_SYS_NS16550_CLK 100000000 220 #endif 221 #define CONFIG_CONS_INDEX 1 222 #define CONFIG_BAUDRATE 115200 223 224 /* 225 * USB 226 */ 227 #ifdef CONFIG_CMD_USB 228 #define CONFIG_USB_DWC2 229 #define CONFIG_USB_STORAGE 230 /* 231 * NOTE: User must define either of the following to select which 232 * of the two USB controllers available on SoCFPGA to use. 233 * The DWC2 driver doesn't support multiple USB controllers. 234 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS 235 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS 236 */ 237 #endif 238 239 /* 240 * USB Gadget (DFU, UMS) 241 */ 242 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 243 #define CONFIG_USB_GADGET 244 #define CONFIG_USB_GADGET_S3C_UDC_OTG 245 #define CONFIG_USB_GADGET_DUALSPEED 246 #define CONFIG_USB_GADGET_VBUS_DRAW 2 247 248 /* USB Composite download gadget - g_dnl */ 249 #define CONFIG_USBDOWNLOAD_GADGET 250 #define CONFIG_USB_GADGET_MASS_STORAGE 251 252 #define CONFIG_DFU_FUNCTION 253 #define CONFIG_DFU_MMC 254 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 255 #define DFU_DEFAULT_POLL_TIMEOUT 300 256 257 /* USB IDs */ 258 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ 259 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ 260 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM 261 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM 262 #ifndef CONFIG_G_DNL_MANUFACTURER 263 #define CONFIG_G_DNL_MANUFACTURER "Altera" 264 #endif 265 #endif 266 267 /* 268 * U-Boot environment 269 */ 270 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 271 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 272 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 273 #define CONFIG_ENV_IS_NOWHERE 274 #define CONFIG_ENV_SIZE 4096 275 276 /* 277 * SPL 278 * 279 * SRAM Memory layout: 280 * 281 * 0xFFFF_0000 ...... Start of SRAM 282 * 0xFFFF_xxxx ...... Top of stack (grows down) 283 * 0xFFFF_yyyy ...... Malloc area 284 * 0xFFFF_zzzz ...... Global Data 285 * 0xFFFF_FF00 ...... End of SRAM 286 */ 287 #define CONFIG_SPL_FRAMEWORK 288 #define CONFIG_SPL_BOARD_INIT 289 #define CONFIG_SPL_RAM_DEVICE 290 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 291 #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR 292 #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) 293 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 294 295 #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ 296 #define CONFIG_CRC32_VERIFY 297 298 /* Linker script for SPL */ 299 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-socfpga/u-boot-spl.lds" 300 301 #define CONFIG_SPL_LIBCOMMON_SUPPORT 302 #define CONFIG_SPL_LIBGENERIC_SUPPORT 303 #define CONFIG_SPL_WATCHDOG_SUPPORT 304 #define CONFIG_SPL_SERIAL_SUPPORT 305 306 /* 307 * Stack setup 308 */ 309 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 310 311 #ifdef CONFIG_SPL_BUILD 312 #undef CONFIG_PARTITIONS 313 #endif 314 315 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ 316