11a2621baSYoshihiro Shimoda /* 21a2621baSYoshihiro Shimoda * Configuation settings for the sh7752evb board 31a2621baSYoshihiro Shimoda * 41a2621baSYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 51a2621baSYoshihiro Shimoda * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 71a2621baSYoshihiro Shimoda */ 81a2621baSYoshihiro Shimoda 91a2621baSYoshihiro Shimoda #ifndef __SH7752EVB_H 101a2621baSYoshihiro Shimoda #define __SH7752EVB_H 111a2621baSYoshihiro Shimoda 121a2621baSYoshihiro Shimoda #undef DEBUG 131a2621baSYoshihiro Shimoda #define CONFIG_SH 1 141a2621baSYoshihiro Shimoda #define CONFIG_SH4A 1 151a2621baSYoshihiro Shimoda #define CONFIG_SH_32BIT 1 161a2621baSYoshihiro Shimoda #define CONFIG_CPU_SH7752 1 171a2621baSYoshihiro Shimoda #define CONFIG_SH7752EVB 1 181a2621baSYoshihiro Shimoda 191a2621baSYoshihiro Shimoda #define CONFIG_SYS_TEXT_BASE 0x5ff80000 201a2621baSYoshihiro Shimoda #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds" 211a2621baSYoshihiro Shimoda 221a2621baSYoshihiro Shimoda #define CONFIG_CMD_MEMORY 231a2621baSYoshihiro Shimoda #define CONFIG_CMD_NET 241a2621baSYoshihiro Shimoda #define CONFIG_CMD_MII 251a2621baSYoshihiro Shimoda #define CONFIG_CMD_PING 261a2621baSYoshihiro Shimoda #define CONFIG_CMD_NFS 271a2621baSYoshihiro Shimoda #define CONFIG_CMD_DFL 281a2621baSYoshihiro Shimoda #define CONFIG_CMD_SDRAM 291a2621baSYoshihiro Shimoda #define CONFIG_CMD_SF 301a2621baSYoshihiro Shimoda #define CONFIG_CMD_RUN 311a2621baSYoshihiro Shimoda #define CONFIG_CMD_SAVEENV 321a2621baSYoshihiro Shimoda #define CONFIG_CMD_MD5SUM 331a2621baSYoshihiro Shimoda #define CONFIG_MD5 341a2621baSYoshihiro Shimoda #define CONFIG_CMD_LOADS 351a2621baSYoshihiro Shimoda #define CONFIG_CMD_MMC 361a2621baSYoshihiro Shimoda #define CONFIG_CMD_EXT2 371a2621baSYoshihiro Shimoda #define CONFIG_DOS_PARTITION 381a2621baSYoshihiro Shimoda #define CONFIG_MAC_PARTITION 391a2621baSYoshihiro Shimoda 401a2621baSYoshihiro Shimoda #define CONFIG_BAUDRATE 115200 411a2621baSYoshihiro Shimoda #define CONFIG_BOOTDELAY 3 421a2621baSYoshihiro Shimoda #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 431a2621baSYoshihiro Shimoda 441a2621baSYoshihiro Shimoda #define CONFIG_VERSION_VARIABLE 451a2621baSYoshihiro Shimoda #undef CONFIG_SHOW_BOOT_PROGRESS 461a2621baSYoshihiro Shimoda #define CONFIG_CMDLINE_EDITING 471a2621baSYoshihiro Shimoda #define CONFIG_AUTO_COMPLETE 481a2621baSYoshihiro Shimoda 491a2621baSYoshihiro Shimoda /* MEMORY */ 501a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_BASE (0x40000000) 511a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024) 521a2621baSYoshihiro Shimoda 531a2621baSYoshihiro Shimoda #define CONFIG_SYS_LONGHELP 541a2621baSYoshihiro Shimoda #define CONFIG_SYS_PROMPT "=> " 551a2621baSYoshihiro Shimoda #define CONFIG_SYS_CBSIZE 256 561a2621baSYoshihiro Shimoda #define CONFIG_SYS_PBSIZE 256 571a2621baSYoshihiro Shimoda #define CONFIG_SYS_MAXARGS 16 581a2621baSYoshihiro Shimoda #define CONFIG_SYS_BARGSIZE 512 591a2621baSYoshihiro Shimoda #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 601a2621baSYoshihiro Shimoda 611a2621baSYoshihiro Shimoda /* SCIF */ 621a2621baSYoshihiro Shimoda #define CONFIG_SCIF_CONSOLE 1 631a2621baSYoshihiro Shimoda #define CONFIG_CONS_SCIF2 1 641a2621baSYoshihiro Shimoda #undef CONFIG_SYS_CONSOLE_INFO_QUIET 651a2621baSYoshihiro Shimoda #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 661a2621baSYoshihiro Shimoda #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 671a2621baSYoshihiro Shimoda 681a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) 691a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 701a2621baSYoshihiro Shimoda 480 * 1024 * 1024) 711a2621baSYoshihiro Shimoda #undef CONFIG_SYS_ALT_MEMTEST 721a2621baSYoshihiro Shimoda #undef CONFIG_SYS_MEMTEST_SCRATCH 731a2621baSYoshihiro Shimoda #undef CONFIG_SYS_LOADS_BAUD_CHANGE 741a2621baSYoshihiro Shimoda 751a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) 761a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE) 771a2621baSYoshihiro Shimoda #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 781a2621baSYoshihiro Shimoda 128 * 1024 * 1024) 791a2621baSYoshihiro Shimoda 801a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_BASE 0x00000000 811a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 821a2621baSYoshihiro Shimoda #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 831a2621baSYoshihiro Shimoda #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 841a2621baSYoshihiro Shimoda 851a2621baSYoshihiro Shimoda /* FLASH */ 861a2621baSYoshihiro Shimoda #define CONFIG_SYS_NO_FLASH 871a2621baSYoshihiro Shimoda 881a2621baSYoshihiro Shimoda /* Ether */ 891a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER 1 901a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_PORT 0 911a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_ADDR 18 921a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 931a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_GETHER 1 941a2621baSYoshihiro Shimoda #define CONFIG_PHYLIB 951a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII 961a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI 971a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII 981a2621baSYoshihiro Shimoda #define CONFIG_PHY_VITESSE 991a2621baSYoshihiro Shimoda 1001a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000 1011a2621baSYoshihiro Shimoda #define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024) 1021a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI 1031a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_SIZE 17 1041a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_NUM_CH 2 1051a2621baSYoshihiro Shimoda #define CONFIG_BOARD_LATE_INIT 1061a2621baSYoshihiro Shimoda 1071a2621baSYoshihiro Shimoda /* SPI */ 1081a2621baSYoshihiro Shimoda #define CONFIG_SH_SPI 1 1091a2621baSYoshihiro Shimoda #define CONFIG_SH_SPI_BASE 0xfe002000 1101a2621baSYoshihiro Shimoda #define CONFIG_SPI_FLASH 1111a2621baSYoshihiro Shimoda #define CONFIG_SPI_FLASH_STMICRO 1 1121a2621baSYoshihiro Shimoda #define CONFIG_SPI_FLASH_MACRONIX 1 1131a2621baSYoshihiro Shimoda 1141a2621baSYoshihiro Shimoda /* MMCIF */ 1151a2621baSYoshihiro Shimoda #define CONFIG_MMC 1 1161a2621baSYoshihiro Shimoda #define CONFIG_GENERIC_MMC 1 1171a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF 1 1181a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 1191a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_CLK 48000000 1201a2621baSYoshihiro Shimoda 1211a2621baSYoshihiro Shimoda /* ENV setting */ 1221a2621baSYoshihiro Shimoda #define CONFIG_ENV_IS_EMBEDDED 1231a2621baSYoshihiro Shimoda #define CONFIG_ENV_IS_IN_SPI_FLASH 1241a2621baSYoshihiro Shimoda #define CONFIG_ENV_SECT_SIZE (64 * 1024) 1251a2621baSYoshihiro Shimoda #define CONFIG_ENV_ADDR (0x00080000) 1261a2621baSYoshihiro Shimoda #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 1271a2621baSYoshihiro Shimoda #define CONFIG_ENV_OVERWRITE 1 1281a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 1291a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 1301a2621baSYoshihiro Shimoda #define CONFIG_EXTRA_ENV_SETTINGS \ 1311a2621baSYoshihiro Shimoda "netboot=bootp; bootm\0" 1321a2621baSYoshihiro Shimoda 1331a2621baSYoshihiro Shimoda /* Board Clock */ 1341a2621baSYoshihiro Shimoda #define CONFIG_SYS_CLK_FREQ 48000000 135*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 136*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 1371a2621baSYoshihiro Shimoda #define CONFIG_SYS_TMU_CLK_DIV 4 1381a2621baSYoshihiro Shimoda #define CONFIG_SYS_HZ 1000 1391a2621baSYoshihiro Shimoda #endif /* __SH7752EVB_H */ 140