1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * sbc8548 board configuration file 11 * Please refer to doc/README.sbc8548 for more info. 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * Top level Makefile configuration choices 18 */ 19 #ifdef CONFIG_PCI 20 #define CONFIG_PCI_INDIRECT_BRIDGE 21 #define CONFIG_PCI1 22 #endif 23 24 #ifdef CONFIG_66 25 #define CONFIG_SYS_CLK_DIV 1 26 #endif 27 28 #ifdef CONFIG_33 29 #define CONFIG_SYS_CLK_DIV 2 30 #endif 31 32 #ifdef CONFIG_PCIE 33 #define CONFIG_PCIE1 34 #endif 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_BOOKE 1 /* BOOKE */ 40 #define CONFIG_E500 1 /* BOOKE e500 family */ 41 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 42 43 /* 44 * If you want to boot from the SODIMM flash, instead of the soldered 45 * on flash, set this, and change JP12, SW2:8 accordingly. 46 */ 47 #undef CONFIG_SYS_ALT_BOOT 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #ifdef CONFIG_SYS_ALT_BOOT 51 #define CONFIG_SYS_TEXT_BASE 0xfff00000 52 #else 53 #define CONFIG_SYS_TEXT_BASE 0xfffa0000 54 #endif 55 #endif 56 57 #undef CONFIG_RIO 58 59 #ifdef CONFIG_PCI 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 62 #endif 63 #ifdef CONFIG_PCIE1 64 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 65 #endif 66 67 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 68 #define CONFIG_ENV_OVERWRITE 69 70 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 71 72 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 73 74 /* 75 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 76 */ 77 #ifndef CONFIG_SYS_CLK_DIV 78 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 79 #endif 80 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 81 82 /* 83 * These can be toggled for performance analysis, otherwise use default. 84 */ 85 #define CONFIG_L2_CACHE /* toggle L2 cache */ 86 #define CONFIG_BTB /* toggle branch predition */ 87 88 /* 89 * Only possible on E500 Version 2 or newer cores. 90 */ 91 #define CONFIG_ENABLE_36BIT_PHYS 1 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 95 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 99 #define CONFIG_SYS_CCSRBAR 0xe0000000 100 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 101 102 /* DDR Setup */ 103 #define CONFIG_SYS_FSL_DDR2 104 #undef CONFIG_FSL_DDR_INTERACTIVE 105 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 106 /* 107 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 108 * to collide, meaning you couldn't reliably read either. So 109 * physically remove the LBC PC100 SDRAM module from the board 110 * before enabling the two SPD options below, or check that you 111 * have the hardware fix on your board via "i2c probe" and looking 112 * for a device at 0x53. 113 */ 114 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 115 #undef CONFIG_DDR_SPD 116 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 118 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 119 120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122 #define CONFIG_VERY_BIG_RAM 123 124 #define CONFIG_NUM_DDR_CONTROLLERS 1 125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 126 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 127 128 /* 129 * The hardware fix for the I2C address collision puts the DDR 130 * SPD at 0x53, but if we are running on an older board w/o the 131 * fix, it will still be at 0x51. We check 0x53 1st. 132 */ 133 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 134 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 135 136 /* 137 * Make sure required options are set 138 */ 139 #ifndef CONFIG_SPD_EEPROM 140 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 141 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 142 #endif 143 144 #undef CONFIG_CLOCKS_IN_MHZ 145 146 /* 147 * FLASH on the Local Bus 148 * Two banks, one 8MB the other 64MB, using the CFI driver. 149 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 150 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 151 * 152 * Default: 153 * ec00_0000 efff_ffff 64MB SODIMM 154 * ff80_0000 ffff_ffff 8MB soldered flash 155 * 156 * Alternate: 157 * ef80_0000 efff_ffff 8MB soldered flash 158 * fc00_0000 ffff_ffff 64MB SODIMM 159 * 160 * BR0_8M: 161 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 162 * Port Size = 8 bits = BRx[19:20] = 01 163 * Use GPCM = BRx[24:26] = 000 164 * Valid = BRx[31] = 1 165 * 166 * BR0_64M: 167 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 168 * Port Size = 32 bits = BRx[19:20] = 11 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 172 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 173 */ 174 #define CONFIG_SYS_BR0_8M 0xff800801 175 #define CONFIG_SYS_BR0_64M 0xfc001801 176 177 /* 178 * BR6_8M: 179 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 180 * Port Size = 8 bits = BRx[19:20] = 01 181 * Use GPCM = BRx[24:26] = 000 182 * Valid = BRx[31] = 1 183 184 * BR6_64M: 185 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 186 * Port Size = 32 bits = BRx[19:20] = 11 187 * 188 * 0 4 8 12 16 20 24 28 189 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 190 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 191 */ 192 #define CONFIG_SYS_BR6_8M 0xef800801 193 #define CONFIG_SYS_BR6_64M 0xec001801 194 195 /* 196 * OR0_8M: 197 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 198 * XAM = OR0[17:18] = 11 199 * CSNT = OR0[20] = 1 200 * ACS = half cycle delay = OR0[21:22] = 11 201 * SCY = 6 = OR0[24:27] = 0110 202 * TRLX = use relaxed timing = OR0[29] = 1 203 * EAD = use external address latch delay = OR0[31] = 1 204 * 205 * OR0_64M: 206 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 207 * 208 * 209 * 0 4 8 12 16 20 24 28 210 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 211 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 212 */ 213 #define CONFIG_SYS_OR0_8M 0xff806e65 214 #define CONFIG_SYS_OR0_64M 0xfc006e65 215 216 /* 217 * OR6_8M: 218 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 219 * XAM = OR6[17:18] = 11 220 * CSNT = OR6[20] = 1 221 * ACS = half cycle delay = OR6[21:22] = 11 222 * SCY = 6 = OR6[24:27] = 0110 223 * TRLX = use relaxed timing = OR6[29] = 1 224 * EAD = use external address latch delay = OR6[31] = 1 225 * 226 * OR6_64M: 227 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 228 * 229 * 0 4 8 12 16 20 24 28 230 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 231 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 232 */ 233 #define CONFIG_SYS_OR6_8M 0xff806e65 234 #define CONFIG_SYS_OR6_64M 0xfc006e65 235 236 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 237 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 238 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 239 240 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 241 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 242 243 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 244 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 245 #else /* JP12 in alternate position */ 246 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 247 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 248 249 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 250 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 251 252 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 253 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 254 #endif 255 256 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 257 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 258 CONFIG_SYS_ALT_FLASH} 259 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 261 #undef CONFIG_SYS_FLASH_CHECKSUM 262 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 263 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 264 265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 266 267 #define CONFIG_FLASH_CFI_DRIVER 268 #define CONFIG_SYS_FLASH_CFI 269 #define CONFIG_SYS_FLASH_EMPTY_INFO 270 271 /* CS5 = Local bus peripherals controlled by the EPLD */ 272 273 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 274 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 275 #define CONFIG_SYS_EPLD_BASE 0xf8000000 276 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 277 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 278 #define CONFIG_SYS_BD_REV 0xf8300000 279 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 280 281 /* 282 * SDRAM on the Local Bus (CS3 and CS4) 283 * Note that most boards have a hardware errata where both the 284 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 285 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 286 * A hardware workaround is also available, see README.sbc8548 file. 287 */ 288 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 289 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 290 291 /* 292 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 293 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 294 * 295 * For BR3, need: 296 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 297 * port-size = 32-bits = BR2[19:20] = 11 298 * no parity checking = BR2[21:22] = 00 299 * SDRAM for MSEL = BR2[24:26] = 011 300 * Valid = BR[31] = 1 301 * 302 * 0 4 8 12 16 20 24 28 303 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 304 * 305 */ 306 307 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 308 309 /* 310 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 311 * 312 * For OR3, need: 313 * 64MB mask for AM, OR3[0:7] = 1111 1100 314 * XAM, OR3[17:18] = 11 315 * 10 columns OR3[19-21] = 011 316 * 12 rows OR3[23-25] = 011 317 * EAD set for extra time OR[31] = 0 318 * 319 * 0 4 8 12 16 20 24 28 320 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 321 */ 322 323 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 324 325 /* 326 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 327 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 328 * 329 * For BR4, need: 330 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 331 * port-size = 32-bits = BR2[19:20] = 11 332 * no parity checking = BR2[21:22] = 00 333 * SDRAM for MSEL = BR2[24:26] = 011 334 * Valid = BR[31] = 1 335 * 336 * 0 4 8 12 16 20 24 28 337 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 338 * 339 */ 340 341 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 342 343 /* 344 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 345 * 346 * For OR4, need: 347 * 64MB mask for AM, OR3[0:7] = 1111 1100 348 * XAM, OR3[17:18] = 11 349 * 10 columns OR3[19-21] = 011 350 * 12 rows OR3[23-25] = 011 351 * EAD set for extra time OR[31] = 0 352 * 353 * 0 4 8 12 16 20 24 28 354 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 355 */ 356 357 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 358 359 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 360 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 361 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 362 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 363 364 /* 365 * Common settings for all Local Bus SDRAM commands. 366 */ 367 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 368 | LSDMR_BSMA1516 \ 369 | LSDMR_PRETOACT3 \ 370 | LSDMR_ACTTORW3 \ 371 | LSDMR_BUFCMD \ 372 | LSDMR_BL8 \ 373 | LSDMR_WRC2 \ 374 | LSDMR_CL3 \ 375 ) 376 377 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 378 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 379 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 380 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 381 #define CONFIG_SYS_LBC_LSDMR_MRW \ 382 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 383 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 384 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 385 386 #define CONFIG_SYS_INIT_RAM_LOCK 1 387 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 388 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 389 390 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 391 392 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 393 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 394 395 /* 396 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 397 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 398 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 399 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 400 * thing for MONITOR_LEN in both cases. 401 */ 402 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 403 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 404 405 /* Serial Port */ 406 #define CONFIG_CONS_INDEX 1 407 #define CONFIG_SYS_NS16550_SERIAL 408 #define CONFIG_SYS_NS16550_REG_SIZE 1 409 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 410 411 #define CONFIG_SYS_BAUDRATE_TABLE \ 412 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 413 414 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 415 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 416 417 /* 418 * I2C 419 */ 420 #define CONFIG_SYS_I2C 421 #define CONFIG_SYS_I2C_FSL 422 #define CONFIG_SYS_FSL_I2C_SPEED 400000 423 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 425 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 426 427 /* 428 * General PCI 429 * Memory space is mapped 1-1, but I/O space must start from 0. 430 */ 431 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 432 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 433 434 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 435 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 436 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 437 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 438 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 439 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 440 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 441 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 442 443 #ifdef CONFIG_PCIE1 444 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 445 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 446 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 447 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 448 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 449 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 451 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 452 #endif 453 454 #ifdef CONFIG_RIO 455 /* 456 * RapidIO MMU 457 */ 458 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 459 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 460 #endif 461 462 #if defined(CONFIG_PCI) 463 #undef CONFIG_EEPRO100 464 #undef CONFIG_TULIP 465 466 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 467 468 #endif /* CONFIG_PCI */ 469 470 #if defined(CONFIG_TSEC_ENET) 471 472 #define CONFIG_MII 1 /* MII PHY management */ 473 #define CONFIG_TSEC1 1 474 #define CONFIG_TSEC1_NAME "eTSEC0" 475 #define CONFIG_TSEC2 1 476 #define CONFIG_TSEC2_NAME "eTSEC1" 477 #undef CONFIG_MPC85XX_FEC 478 479 #define TSEC1_PHY_ADDR 0x19 480 #define TSEC2_PHY_ADDR 0x1a 481 482 #define TSEC1_PHYIDX 0 483 #define TSEC2_PHYIDX 0 484 485 #define TSEC1_FLAGS TSEC_GIGABIT 486 #define TSEC2_FLAGS TSEC_GIGABIT 487 488 /* Options are: eTSEC[0-3] */ 489 #define CONFIG_ETHPRIME "eTSEC0" 490 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 491 #endif /* CONFIG_TSEC_ENET */ 492 493 /* 494 * Environment 495 */ 496 #define CONFIG_ENV_IS_IN_FLASH 1 497 #define CONFIG_ENV_SIZE 0x2000 498 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 499 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 500 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 501 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 502 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 503 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 504 #else 505 #warning undefined environment size/location. 506 #endif 507 508 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 509 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 510 511 /* 512 * BOOTP options 513 */ 514 #define CONFIG_BOOTP_BOOTFILESIZE 515 #define CONFIG_BOOTP_BOOTPATH 516 #define CONFIG_BOOTP_GATEWAY 517 #define CONFIG_BOOTP_HOSTNAME 518 519 /* 520 * Command line configuration. 521 */ 522 #define CONFIG_CMD_REGINFO 523 524 #if defined(CONFIG_PCI) 525 #define CONFIG_CMD_PCI 526 #endif 527 528 #undef CONFIG_WATCHDOG /* watchdog disabled */ 529 530 /* 531 * Miscellaneous configurable options 532 */ 533 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 534 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 535 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 536 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 537 #if defined(CONFIG_CMD_KGDB) 538 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 539 #else 540 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 541 #endif 542 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 543 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 544 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 545 546 /* 547 * For booting Linux, the board info and command line data 548 * have to be in the first 8 MB of memory, since this is 549 * the maximum mapped by the Linux kernel during initialization. 550 */ 551 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 552 553 #if defined(CONFIG_CMD_KGDB) 554 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 555 #endif 556 557 /* 558 * Environment Configuration 559 */ 560 #if defined(CONFIG_TSEC_ENET) 561 #define CONFIG_HAS_ETH0 562 #define CONFIG_HAS_ETH1 563 #endif 564 565 #define CONFIG_IPADDR 192.168.0.55 566 567 #define CONFIG_HOSTNAME sbc8548 568 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 569 #define CONFIG_BOOTFILE "/uImage" 570 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 571 572 #define CONFIG_SERVERIP 192.168.0.2 573 #define CONFIG_GATEWAYIP 192.168.0.1 574 #define CONFIG_NETMASK 255.255.255.0 575 576 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 577 578 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 579 580 #define CONFIG_BAUDRATE 115200 581 582 #define CONFIG_EXTRA_ENV_SETTINGS \ 583 "netdev=eth0\0" \ 584 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 585 "tftpflash=tftpboot $loadaddr $uboot; " \ 586 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 587 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 588 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 589 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 590 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 591 "consoledev=ttyS0\0" \ 592 "ramdiskaddr=2000000\0" \ 593 "ramdiskfile=uRamdisk\0" \ 594 "fdtaddr=1e00000\0" \ 595 "fdtfile=sbc8548.dtb\0" 596 597 #define CONFIG_NFSBOOTCOMMAND \ 598 "setenv bootargs root=/dev/nfs rw " \ 599 "nfsroot=$serverip:$rootpath " \ 600 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 601 "console=$consoledev,$baudrate $othbootargs;" \ 602 "tftp $loadaddr $bootfile;" \ 603 "tftp $fdtaddr $fdtfile;" \ 604 "bootm $loadaddr - $fdtaddr" 605 606 #define CONFIG_RAMBOOTCOMMAND \ 607 "setenv bootargs root=/dev/ram rw " \ 608 "console=$consoledev,$baudrate $othbootargs;" \ 609 "tftp $ramdiskaddr $ramdiskfile;" \ 610 "tftp $loadaddr $bootfile;" \ 611 "tftp $fdtaddr $fdtfile;" \ 612 "bootm $loadaddr $ramdiskaddr $fdtaddr" 613 614 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 615 616 #endif /* __CONFIG_H */ 617