1 /* 2 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 3 * Copyright 2007 Embedded Specialties, Inc. 4 * Copyright 2004, 2007 Freescale Semiconductor. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * sbc8548 board configuration file 27 * Please refer to doc/README.sbc8548 for more info. 28 */ 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * Top level Makefile configuration choices 34 */ 35 #ifdef CONFIG_PCI 36 #define CONFIG_PCI1 37 #endif 38 39 #ifdef CONFIG_66 40 #define CONFIG_SYS_CLK_DIV 1 41 #endif 42 43 #ifdef CONFIG_33 44 #define CONFIG_SYS_CLK_DIV 2 45 #endif 46 47 #ifdef CONFIG_PCIE 48 #define CONFIG_PCIE1 49 #endif 50 51 /* 52 * High Level Configuration Options 53 */ 54 #define CONFIG_BOOKE 1 /* BOOKE */ 55 #define CONFIG_E500 1 /* BOOKE e500 family */ 56 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 57 #define CONFIG_MPC8548 1 /* MPC8548 specific */ 58 #define CONFIG_SBC8548 1 /* SBC8548 board specific */ 59 60 #undef CONFIG_RIO 61 62 #ifdef CONFIG_PCI 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 65 #endif 66 #ifdef CONFIG_PCIE1 67 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 68 #endif 69 70 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 71 #define CONFIG_ENV_OVERWRITE 72 73 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 74 75 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 76 77 /* 78 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 79 */ 80 #ifndef CONFIG_SYS_CLK_DIV 81 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 82 #endif 83 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 84 85 /* 86 * These can be toggled for performance analysis, otherwise use default. 87 */ 88 #define CONFIG_L2_CACHE /* toggle L2 cache */ 89 #define CONFIG_BTB /* toggle branch predition */ 90 91 /* 92 * Only possible on E500 Version 2 or newer cores. 93 */ 94 #define CONFIG_ENABLE_36BIT_PHYS 1 95 96 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 97 98 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 99 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 100 #define CONFIG_SYS_MEMTEST_END 0x00400000 101 102 /* 103 * Base addresses -- Note these are effective addresses where the 104 * actual resources get mapped (not physical addresses) 105 */ 106 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 107 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 108 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 109 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 110 111 /* DDR Setup */ 112 #define CONFIG_FSL_DDR2 113 #undef CONFIG_FSL_DDR_INTERACTIVE 114 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 115 #undef CONFIG_DDR_SPD 116 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 117 118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 119 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 120 121 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 122 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 123 #define CONFIG_VERY_BIG_RAM 124 125 #define CONFIG_NUM_DDR_CONTROLLERS 1 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 127 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 128 129 /* I2C addresses of SPD EEPROMs */ 130 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 131 132 /* 133 * Make sure required options are set 134 */ 135 #ifndef CONFIG_SPD_EEPROM 136 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 137 #endif 138 139 #undef CONFIG_CLOCKS_IN_MHZ 140 141 /* 142 * FLASH on the Local Bus 143 * Two banks, one 8MB the other 64MB, using the CFI driver. 144 * Boot from BR0/OR0 bank at 0xff80_0000 145 * Alternate BR6/OR6 bank at 0xfb80_0000 146 * 147 * BR0: 148 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 149 * Port Size = 8 bits = BRx[19:20] = 01 150 * Use GPCM = BRx[24:26] = 000 151 * Valid = BRx[31] = 1 152 * 153 * 0 4 8 12 16 20 24 28 154 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 155 * 156 * BR6: 157 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 158 * Port Size = 32 bits = BRx[19:20] = 11 159 * Use GPCM = BRx[24:26] = 000 160 * Valid = BRx[31] = 1 161 * 162 * 0 4 8 12 16 20 24 28 163 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 164 * 165 * OR0: 166 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 167 * XAM = OR0[17:18] = 11 168 * CSNT = OR0[20] = 1 169 * ACS = half cycle delay = OR0[21:22] = 11 170 * SCY = 6 = OR0[24:27] = 0110 171 * TRLX = use relaxed timing = OR0[29] = 1 172 * EAD = use external address latch delay = OR0[31] = 1 173 * 174 * 0 4 8 12 16 20 24 28 175 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 176 * 177 * OR6: 178 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 179 * XAM = OR6[17:18] = 11 180 * CSNT = OR6[20] = 1 181 * ACS = half cycle delay = OR6[21:22] = 11 182 * SCY = 6 = OR6[24:27] = 0110 183 * TRLX = use relaxed timing = OR6[29] = 1 184 * EAD = use external address latch delay = OR6[31] = 1 185 * 186 * 0 4 8 12 16 20 24 28 187 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 188 */ 189 190 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 191 #define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ 192 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ 193 194 #define CONFIG_SYS_BR0_PRELIM 0xff800801 195 #define CONFIG_SYS_BR6_PRELIM 0xfb801801 196 197 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 198 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 199 200 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 201 CONFIG_SYS_ALT_FLASH} 202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 203 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 204 #undef CONFIG_SYS_FLASH_CHECKSUM 205 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 207 208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 209 210 #define CONFIG_FLASH_CFI_DRIVER 211 #define CONFIG_SYS_FLASH_CFI 212 #define CONFIG_SYS_FLASH_EMPTY_INFO 213 214 /* CS5 = Local bus peripherals controlled by the EPLD */ 215 216 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 217 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 218 #define CONFIG_SYS_EPLD_BASE 0xf8000000 219 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 220 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 221 #define CONFIG_SYS_BD_REV 0xf8300000 222 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 223 224 /* 225 * SDRAM on the Local Bus (CS3 and CS4) 226 */ 227 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 228 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 229 230 /* 231 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 232 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 233 * 234 * For BR3, need: 235 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 236 * port-size = 32-bits = BR2[19:20] = 11 237 * no parity checking = BR2[21:22] = 00 238 * SDRAM for MSEL = BR2[24:26] = 011 239 * Valid = BR[31] = 1 240 * 241 * 0 4 8 12 16 20 24 28 242 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 243 * 244 */ 245 246 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 247 248 /* 249 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 250 * 251 * For OR3, need: 252 * 64MB mask for AM, OR3[0:7] = 1111 1100 253 * XAM, OR3[17:18] = 11 254 * 10 columns OR3[19-21] = 011 255 * 12 rows OR3[23-25] = 011 256 * EAD set for extra time OR[31] = 0 257 * 258 * 0 4 8 12 16 20 24 28 259 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 260 */ 261 262 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 263 264 /* 265 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 266 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 267 * 268 * For BR4, need: 269 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 270 * port-size = 32-bits = BR2[19:20] = 11 271 * no parity checking = BR2[21:22] = 00 272 * SDRAM for MSEL = BR2[24:26] = 011 273 * Valid = BR[31] = 1 274 * 275 * 0 4 8 12 16 20 24 28 276 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 277 * 278 */ 279 280 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 281 282 /* 283 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 284 * 285 * For OR4, need: 286 * 64MB mask for AM, OR3[0:7] = 1111 1100 287 * XAM, OR3[17:18] = 11 288 * 10 columns OR3[19-21] = 011 289 * 12 rows OR3[23-25] = 011 290 * EAD set for extra time OR[31] = 0 291 * 292 * 0 4 8 12 16 20 24 28 293 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 294 */ 295 296 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 297 298 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 299 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 300 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 301 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 302 303 /* 304 * Common settings for all Local Bus SDRAM commands. 305 * At run time, either BSMA1516 (for CPU 1.1) 306 * or BSMA1617 (for CPU 1.0) (old) 307 * is OR'ed in too. 308 */ 309 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 310 | LSDMR_PRETOACT7 \ 311 | LSDMR_ACTTORW7 \ 312 | LSDMR_BL8 \ 313 | LSDMR_WRC4 \ 314 | LSDMR_CL3 \ 315 | LSDMR_RFEN \ 316 ) 317 318 #define CONFIG_SYS_INIT_RAM_LOCK 1 319 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 320 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 321 322 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 323 324 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 325 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 326 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 327 328 /* 329 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 330 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 331 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 332 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 333 * thing for MONITOR_LEN in both cases. 334 */ 335 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 336 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 337 338 /* Serial Port */ 339 #define CONFIG_CONS_INDEX 1 340 #define CONFIG_SYS_NS16550 341 #define CONFIG_SYS_NS16550_SERIAL 342 #define CONFIG_SYS_NS16550_REG_SIZE 1 343 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 344 345 #define CONFIG_SYS_BAUDRATE_TABLE \ 346 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 347 348 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 349 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 350 351 /* Use the HUSH parser */ 352 #define CONFIG_SYS_HUSH_PARSER 353 #ifdef CONFIG_SYS_HUSH_PARSER 354 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 355 #endif 356 357 /* pass open firmware flat tree */ 358 #define CONFIG_OF_LIBFDT 1 359 #define CONFIG_OF_BOARD_SETUP 1 360 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 361 362 /* 363 * I2C 364 */ 365 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 366 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 367 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 368 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 369 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 370 #define CONFIG_SYS_I2C_SLAVE 0x7F 371 #define CONFIG_SYS_I2C_OFFSET 0x3000 372 373 /* 374 * General PCI 375 * Memory space is mapped 1-1, but I/O space must start from 0. 376 */ 377 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 378 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 379 380 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 381 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 382 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 383 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 384 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 385 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 386 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 387 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 388 389 #ifdef CONFIG_PCIE1 390 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 391 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 392 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 393 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 394 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 395 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 396 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 397 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 398 #endif 399 400 #ifdef CONFIG_RIO 401 /* 402 * RapidIO MMU 403 */ 404 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 405 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 406 #endif 407 408 #if defined(CONFIG_PCI) 409 410 #define CONFIG_NET_MULTI 411 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 412 413 #undef CONFIG_EEPRO100 414 #undef CONFIG_TULIP 415 416 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 417 418 #endif /* CONFIG_PCI */ 419 420 421 #if defined(CONFIG_TSEC_ENET) 422 423 #ifndef CONFIG_NET_MULTI 424 #define CONFIG_NET_MULTI 1 425 #endif 426 427 #define CONFIG_MII 1 /* MII PHY management */ 428 #define CONFIG_TSEC1 1 429 #define CONFIG_TSEC1_NAME "eTSEC0" 430 #define CONFIG_TSEC2 1 431 #define CONFIG_TSEC2_NAME "eTSEC1" 432 #undef CONFIG_MPC85XX_FEC 433 434 #define TSEC1_PHY_ADDR 0x19 435 #define TSEC2_PHY_ADDR 0x1a 436 437 #define TSEC1_PHYIDX 0 438 #define TSEC2_PHYIDX 0 439 440 #define TSEC1_FLAGS TSEC_GIGABIT 441 #define TSEC2_FLAGS TSEC_GIGABIT 442 443 /* Options are: eTSEC[0-3] */ 444 #define CONFIG_ETHPRIME "eTSEC0" 445 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 446 #endif /* CONFIG_TSEC_ENET */ 447 448 /* 449 * Environment 450 */ 451 #define CONFIG_ENV_IS_IN_FLASH 1 452 #define CONFIG_ENV_SIZE 0x2000 453 #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ 454 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) 455 #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ 456 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ 457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 458 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 459 #else 460 #warning undefined environment size/location. 461 #endif 462 463 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 464 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 465 466 /* 467 * BOOTP options 468 */ 469 #define CONFIG_BOOTP_BOOTFILESIZE 470 #define CONFIG_BOOTP_BOOTPATH 471 #define CONFIG_BOOTP_GATEWAY 472 #define CONFIG_BOOTP_HOSTNAME 473 474 475 /* 476 * Command line configuration. 477 */ 478 #include <config_cmd_default.h> 479 480 #define CONFIG_CMD_PING 481 #define CONFIG_CMD_I2C 482 #define CONFIG_CMD_MII 483 #define CONFIG_CMD_ELF 484 #define CONFIG_CMD_REGINFO 485 486 #if defined(CONFIG_PCI) 487 #define CONFIG_CMD_PCI 488 #endif 489 490 491 #undef CONFIG_WATCHDOG /* watchdog disabled */ 492 493 /* 494 * Miscellaneous configurable options 495 */ 496 #define CONFIG_CMDLINE_EDITING /* undef to save memory */ 497 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 498 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 499 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 500 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 501 #if defined(CONFIG_CMD_KGDB) 502 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 503 #else 504 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 505 #endif 506 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 507 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 508 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 509 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 510 511 /* 512 * For booting Linux, the board info and command line data 513 * have to be in the first 8 MB of memory, since this is 514 * the maximum mapped by the Linux kernel during initialization. 515 */ 516 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 517 518 /* 519 * Internal Definitions 520 * 521 * Boot Flags 522 */ 523 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 524 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 525 526 #if defined(CONFIG_CMD_KGDB) 527 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 528 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 529 #endif 530 531 /* 532 * Environment Configuration 533 */ 534 535 /* The mac addresses for all ethernet interface */ 536 #if defined(CONFIG_TSEC_ENET) 537 #define CONFIG_HAS_ETH0 538 #define CONFIG_ETHADDR 02:E0:0C:00:00:FD 539 #define CONFIG_HAS_ETH1 540 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD 541 #endif 542 543 #define CONFIG_IPADDR 192.168.0.55 544 545 #define CONFIG_HOSTNAME sbc8548 546 #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx 547 #define CONFIG_BOOTFILE /uImage 548 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 549 550 #define CONFIG_SERVERIP 192.168.0.2 551 #define CONFIG_GATEWAYIP 192.168.0.1 552 #define CONFIG_NETMASK 255.255.255.0 553 554 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 555 556 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 557 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 558 559 #define CONFIG_BAUDRATE 115200 560 561 #define CONFIG_EXTRA_ENV_SETTINGS \ 562 "netdev=eth0\0" \ 563 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 564 "tftpflash=tftpboot $loadaddr $uboot; " \ 565 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 566 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 567 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 568 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 569 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 570 "consoledev=ttyS0\0" \ 571 "ramdiskaddr=2000000\0" \ 572 "ramdiskfile=uRamdisk\0" \ 573 "fdtaddr=c00000\0" \ 574 "fdtfile=sbc8548.dtb\0" 575 576 #define CONFIG_NFSBOOTCOMMAND \ 577 "setenv bootargs root=/dev/nfs rw " \ 578 "nfsroot=$serverip:$rootpath " \ 579 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 580 "console=$consoledev,$baudrate $othbootargs;" \ 581 "tftp $loadaddr $bootfile;" \ 582 "tftp $fdtaddr $fdtfile;" \ 583 "bootm $loadaddr - $fdtaddr" 584 585 586 #define CONFIG_RAMBOOTCOMMAND \ 587 "setenv bootargs root=/dev/ram rw " \ 588 "console=$consoledev,$baudrate $othbootargs;" \ 589 "tftp $ramdiskaddr $ramdiskfile;" \ 590 "tftp $loadaddr $bootfile;" \ 591 "tftp $fdtaddr $fdtfile;" \ 592 "bootm $loadaddr $ramdiskaddr $fdtaddr" 593 594 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 595 596 #endif /* __CONFIG_H */ 597