1c133c1fbSYusuke Goda /* 2c133c1fbSYusuke Goda * Configuation settings for the Renesas R7780MP board 3c133c1fbSYusuke Goda * 4ec39d479SNobuhiro Iwamatsu * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5c133c1fbSYusuke Goda * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 6c133c1fbSYusuke Goda * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8c133c1fbSYusuke Goda */ 9c133c1fbSYusuke Goda 10c133c1fbSYusuke Goda #ifndef __R7780RP_H 11c133c1fbSYusuke Goda #define __R7780RP_H 12c133c1fbSYusuke Goda 13c133c1fbSYusuke Goda #undef DEBUG 14c133c1fbSYusuke Goda #define CONFIG_SH 1 15c133c1fbSYusuke Goda #define CONFIG_SH4A 1 16c133c1fbSYusuke Goda #define CONFIG_CPU_SH7780 1 17c133c1fbSYusuke Goda #define CONFIG_R7780MP 1 186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_R7780MP_OLD_FLASH 1 19ec39d479SNobuhiro Iwamatsu #define __LITTLE_ENDIAN__ 1 20c133c1fbSYusuke Goda 21c133c1fbSYusuke Goda /* 22c133c1fbSYusuke Goda * Command line configuration. 23c133c1fbSYusuke Goda */ 24c133c1fbSYusuke Goda #define CONFIG_CMD_SDRAM 25c133c1fbSYusuke Goda #define CONFIG_CMD_FLASH 26c133c1fbSYusuke Goda #define CONFIG_CMD_MEMORY 27c133c1fbSYusuke Goda #define CONFIG_CMD_PCI 28c133c1fbSYusuke Goda #define CONFIG_CMD_NET 29c133c1fbSYusuke Goda #define CONFIG_CMD_PING 30bdab39d3SMike Frysinger #define CONFIG_CMD_SAVEENV 31c133c1fbSYusuke Goda #define CONFIG_CMD_NFS 32c133c1fbSYusuke Goda #define CONFIG_CMD_IDE 33c133c1fbSYusuke Goda #define CONFIG_CMD_EXT2 34c133c1fbSYusuke Goda #define CONFIG_DOS_PARTITION 35c133c1fbSYusuke Goda 366c58a030SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SCIF_CONSOLE 1 37c133c1fbSYusuke Goda #define CONFIG_BAUDRATE 115200 38c133c1fbSYusuke Goda #define CONFIG_CONS_SCIF0 1 39c133c1fbSYusuke Goda 40c133c1fbSYusuke Goda #define CONFIG_BOOTDELAY 3 41c133c1fbSYusuke Goda #define CONFIG_BOOTARGS "console=ttySC0,115200" 42c133c1fbSYusuke Goda #define CONFIG_ENV_OVERWRITE 1 43c133c1fbSYusuke Goda 44c133c1fbSYusuke Goda /* check for keypress on bootdelay==0 */ 45c133c1fbSYusuke Goda /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ 46c133c1fbSYusuke Goda 47913c8910SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE (0x08000000) 496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 50c133c1fbSYusuke Goda 516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP 526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " 536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE 256 556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE 512 57c133c1fbSYusuke Goda 586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 5914d0a02aSWolfgang Denk #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 60c133c1fbSYusuke Goda 61ec39d479SNobuhiro Iwamatsu /* Flash board support */ 626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE (0xA0000000) 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_R7780MP_OLD_FLASH 64ec39d479SNobuhiro Iwamatsu /* NOR Flash (S29PL127J60TFI130) */ 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_MAX_FLASH_BANKS (2) 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_MAX_FLASH_SECT 270 686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_FLASH_BASE + 0x100000,\ 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_FLASH_BASE + 0x400000,\ 716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_FLASH_BASE + 0x700000, } 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ 73ec39d479SNobuhiro Iwamatsu /* NOR Flash (Spantion S29GL256P) */ 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_MAX_FLASH_BANKS (1) 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_MAX_FLASH_SECT 256 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ 78c133c1fbSYusuke Goda 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 80c133c1fbSYusuke Goda /* Address of u-boot image in Flash */ 816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 83c133c1fbSYusuke Goda /* Size of DRAM reserved for malloc() use */ 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) 85c133c1fbSYusuke Goda 866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RX_ETH_BUFFER (8) 88c133c1fbSYusuke Goda 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 9000b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_QUIET_TEST 93c133c1fbSYusuke Goda /* print 'E' for empty sector on flinfo */ 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 95c133c1fbSYusuke Goda 965a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 970e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE (256 * 1024) 980e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 102c133c1fbSYusuke Goda 103c133c1fbSYusuke Goda /* Board Clock */ 104c133c1fbSYusuke Goda #define CONFIG_SYS_CLK_FREQ 33333333 105*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 106*684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 107be45c632SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TMU_CLK_DIV 4 1088dd29c87SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 109c133c1fbSYusuke Goda 110c133c1fbSYusuke Goda /* PCI Controller */ 111c133c1fbSYusuke Goda #if defined(CONFIG_CMD_PCI) 112c133c1fbSYusuke Goda #define CONFIG_PCI 113c133c1fbSYusuke Goda #define CONFIG_SH4_PCI 114ab8f4d40SNobuhiro Iwamatsu #define CONFIG_SH7780_PCI 11506b18163SYoshihiro Shimoda #define CONFIG_SH7780_PCI_LSR 0x07f00001 11606b18163SYoshihiro Shimoda #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 11706b18163SYoshihiro Shimoda #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 118c133c1fbSYusuke Goda #define CONFIG_PCI_PNP 119c133c1fbSYusuke Goda #define CONFIG_PCI_SCAN_SHOW 1 120c133c1fbSYusuke Goda #define __io 121c133c1fbSYusuke Goda #define __mem_pci 122c133c1fbSYusuke Goda 123c133c1fbSYusuke Goda #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 124c133c1fbSYusuke Goda #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 125c133c1fbSYusuke Goda #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 126c133c1fbSYusuke Goda 127c133c1fbSYusuke Goda #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 128c133c1fbSYusuke Goda #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 129c133c1fbSYusuke Goda #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 13004366d07SNobuhiro Iwamatsu #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 13104366d07SNobuhiro Iwamatsu #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 13204366d07SNobuhiro Iwamatsu #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 133c133c1fbSYusuke Goda #endif /* CONFIG_CMD_PCI */ 134c133c1fbSYusuke Goda 135c133c1fbSYusuke Goda #if defined(CONFIG_CMD_NET) 136ec39d479SNobuhiro Iwamatsu /* 137ec39d479SNobuhiro Iwamatsu #define CONFIG_RTL8169 138ec39d479SNobuhiro Iwamatsu */ 139c7c1dbbfSMarcel Ziswiler /* AX88796L Support(NE2000 base chip) */ 140c133c1fbSYusuke Goda #define CONFIG_DRIVER_AX88796L 141c133c1fbSYusuke Goda #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 142c133c1fbSYusuke Goda #endif 143c133c1fbSYusuke Goda 144c133c1fbSYusuke Goda /* Compact flash Support */ 145c133c1fbSYusuke Goda #if defined(CONFIG_CMD_IDE) 146c133c1fbSYusuke Goda #define CONFIG_IDE_RESET 1 1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIO_MODE 1 1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 1496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 1536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 1546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 155f2a37fcdSAlbert Aribaud #define CONFIG_IDE_SWAP_IO 156c133c1fbSYusuke Goda #endif /* CONFIG_CMD_IDE */ 157c133c1fbSYusuke Goda 158c133c1fbSYusuke Goda #endif /* __R7780RP_H */ 159