1*0963060cSMartyn Welch /* SPDX-License-Identifier: GPL-2.0+ */ 2*0963060cSMartyn Welch /* 3*0963060cSMartyn Welch * Copyright (C) 2018 Collabora Ltd. 4*0963060cSMartyn Welch * 5*0963060cSMartyn Welch * Based on include/configs/xpress.h: 6*0963060cSMartyn Welch * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 7*0963060cSMartyn Welch */ 8*0963060cSMartyn Welch #ifndef __PCL063_H 9*0963060cSMartyn Welch #define __PCL063_H 10*0963060cSMartyn Welch 11*0963060cSMartyn Welch #include <linux/sizes.h> 12*0963060cSMartyn Welch #include "mx6_common.h" 13*0963060cSMartyn Welch 14*0963060cSMartyn Welch /* SPL options */ 15*0963060cSMartyn Welch #include "imx6_spl.h" 16*0963060cSMartyn Welch 17*0963060cSMartyn Welch /* 18*0963060cSMartyn Welch * There is a bug in some i.MX6UL processors that results in the initial 19*0963060cSMartyn Welch * portion of OCRAM being unavailable when booting from (at least) an SD 20*0963060cSMartyn Welch * card. 21*0963060cSMartyn Welch * 22*0963060cSMartyn Welch * Tweak the SPL text base address to avoid this. 23*0963060cSMartyn Welch */ 24*0963060cSMartyn Welch #undef CONFIG_SPL_TEXT_BASE 25*0963060cSMartyn Welch #define CONFIG_SPL_TEXT_BASE 0x00909000 26*0963060cSMartyn Welch 27*0963060cSMartyn Welch /* Size of malloc() pool */ 28*0963060cSMartyn Welch #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) 29*0963060cSMartyn Welch 30*0963060cSMartyn Welch /* Console configs */ 31*0963060cSMartyn Welch #define CONFIG_MXC_UART_BASE UART1_BASE 32*0963060cSMartyn Welch 33*0963060cSMartyn Welch /* MMC Configs */ 34*0963060cSMartyn Welch #define CONFIG_FSL_USDHC 35*0963060cSMartyn Welch 36*0963060cSMartyn Welch #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR 37*0963060cSMartyn Welch 38*0963060cSMartyn Welch /* Miscellaneous configurable options */ 39*0963060cSMartyn Welch #define CONFIG_SYS_MEMTEST_START 0x80000000 40*0963060cSMartyn Welch #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) 41*0963060cSMartyn Welch 42*0963060cSMartyn Welch #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 43*0963060cSMartyn Welch #define CONFIG_SYS_HZ 1000 44*0963060cSMartyn Welch 45*0963060cSMartyn Welch /* Physical Memory Map */ 46*0963060cSMartyn Welch #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 47*0963060cSMartyn Welch #define PHYS_SDRAM_SIZE SZ_256M 48*0963060cSMartyn Welch 49*0963060cSMartyn Welch #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 50*0963060cSMartyn Welch #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 51*0963060cSMartyn Welch #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 52*0963060cSMartyn Welch 53*0963060cSMartyn Welch #define CONFIG_SYS_INIT_SP_OFFSET \ 54*0963060cSMartyn Welch (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 55*0963060cSMartyn Welch #define CONFIG_SYS_INIT_SP_ADDR \ 56*0963060cSMartyn Welch (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 57*0963060cSMartyn Welch 58*0963060cSMartyn Welch #define CONFIG_ENV_SIZE (16 << 10) 59*0963060cSMartyn Welch #define CONFIG_ENV_OFFSET (512 << 10) 60*0963060cSMartyn Welch 61*0963060cSMartyn Welch /* NAND */ 62*0963060cSMartyn Welch #define CONFIG_SYS_MAX_NAND_DEVICE 1 63*0963060cSMartyn Welch #define CONFIG_SYS_NAND_BASE 0x40000000 64*0963060cSMartyn Welch 65*0963060cSMartyn Welch /* USB Configs */ 66*0963060cSMartyn Welch #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 67*0963060cSMartyn Welch #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 68*0963060cSMartyn Welch #define CONFIG_MXC_USB_FLAGS 0 69*0963060cSMartyn Welch #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 70*0963060cSMartyn Welch 71*0963060cSMartyn Welch #define CONFIG_IMX_THERMAL 72*0963060cSMartyn Welch 73*0963060cSMartyn Welch #define CONFIG_EXTRA_ENV_SETTINGS \ 74*0963060cSMartyn Welch "console=ttymxc0,115200n8\0" \ 75*0963060cSMartyn Welch "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 76*0963060cSMartyn Welch "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 77*0963060cSMartyn Welch "fdt_addr_r=0x82000000\0" \ 78*0963060cSMartyn Welch "fdt_high=0xffffffff\0" \ 79*0963060cSMartyn Welch "initrd_high=0xffffffff\0" \ 80*0963060cSMartyn Welch "kernel_addr_r=0x81000000\0" \ 81*0963060cSMartyn Welch "pxefile_addr_r=0x87100000\0" \ 82*0963060cSMartyn Welch "ramdisk_addr_r=0x82100000\0" \ 83*0963060cSMartyn Welch "scriptaddr=0x87000000\0" \ 84*0963060cSMartyn Welch BOOTENV 85*0963060cSMartyn Welch 86*0963060cSMartyn Welch #define BOOT_TARGET_DEVICES(func) \ 87*0963060cSMartyn Welch func(MMC, mmc, 0) \ 88*0963060cSMartyn Welch func(UBIFS, ubifs, 0) \ 89*0963060cSMartyn Welch func(PXE, pxe, na) \ 90*0963060cSMartyn Welch func(DHCP, dhcp, na) 91*0963060cSMartyn Welch 92*0963060cSMartyn Welch #include <config_distro_bootcmd.h> 93*0963060cSMartyn Welch 94*0963060cSMartyn Welch #endif /* __PCL063_H */ 95