1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 #define CONFIG_MP 42 43 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 44 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 45 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 46 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 47 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_SYS_SATA_MAX_DEVICE 2 54 #define CONFIG_LBA48 55 56 #ifndef __ASSEMBLY__ 57 extern unsigned long get_board_sys_clk(unsigned long dummy); 58 #endif 59 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 60 61 #define CONFIG_DDR_CLK_FREQ 66666666 62 63 #define CONFIG_HWCONFIG 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE 68 #define CONFIG_BTB 69 70 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 71 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 72 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 73 74 #define CONFIG_SYS_CCSRBAR 0xffe00000 75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 76 77 /* DDR Setup */ 78 79 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 80 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 81 82 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 85 86 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 87 88 /* Default settings for DDR3 */ 89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 91 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 92 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 93 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 94 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 95 96 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 97 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 98 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 99 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 100 101 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 102 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 103 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 104 #define CONFIG_SYS_DDR_RCW_1 0x00000000 105 #define CONFIG_SYS_DDR_RCW_2 0x00000000 106 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 107 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 108 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 109 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 110 111 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 112 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 113 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 114 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 115 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 116 #define CONFIG_SYS_DDR_MODE_1 0x80461320 117 #define CONFIG_SYS_DDR_MODE_2 0x00008000 118 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 119 120 /* 121 * Memory map 122 * 123 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 124 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 125 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 126 * 127 * Localbus 128 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 129 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 130 * 131 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 132 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 133 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 134 */ 135 136 /* 137 * Local Bus Definitions 138 */ 139 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 140 #define CONFIG_SYS_FLASH_BASE 0xec000000 141 142 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 143 144 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 145 | BR_PS_16 | BR_V) 146 147 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 148 149 #define CONFIG_SYS_SSD_BASE 0xe0000000 150 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 151 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 152 BR_PS_16 | BR_V) 153 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 154 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 155 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 156 157 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 158 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 159 160 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 161 #define CONFIG_SYS_FLASH_QUIET_TEST 162 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 163 164 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 165 166 #undef CONFIG_SYS_FLASH_CHECKSUM 167 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 168 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 169 170 #define CONFIG_FLASH_CFI_DRIVER 171 #define CONFIG_SYS_FLASH_CFI 172 #define CONFIG_SYS_FLASH_EMPTY_INFO 173 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 174 175 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 176 177 #define CONFIG_SYS_INIT_RAM_LOCK 178 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 179 /* Initial L1 address */ 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 183 /* Size of used area in RAM */ 184 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 185 186 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 187 GENERATED_GBL_DATA_SIZE) 188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 189 190 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 191 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 192 193 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 194 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 195 196 /* Serial Port 197 * open - index 2 198 * shorted - index 1 199 */ 200 #define CONFIG_CONS_INDEX 1 201 #undef CONFIG_SERIAL_SOFTWARE_FIFO 202 #define CONFIG_SYS_NS16550_SERIAL 203 #define CONFIG_SYS_NS16550_REG_SIZE 1 204 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 205 206 #define CONFIG_SYS_BAUDRATE_TABLE \ 207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 208 209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 211 212 /* I2C */ 213 #define CONFIG_SYS_I2C 214 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 215 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 216 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 217 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 218 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 219 220 /* 221 * I2C2 EEPROM 222 */ 223 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 224 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 225 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 226 227 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 228 229 /* enable read and write access to EEPROM */ 230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 233 234 /* 235 * eSPI - Enhanced SPI 236 */ 237 #define CONFIG_HARD_SPI 238 239 #if defined(CONFIG_PCI) 240 /* 241 * General PCI 242 * Memory space is mapped 1-1, but I/O space must start from 0. 243 */ 244 245 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 246 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 247 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 248 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 249 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 250 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 251 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 252 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 253 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 254 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 255 256 /* controller 1, tgtid 1, Base address a000 */ 257 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 258 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 259 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 260 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 261 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 262 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 263 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 264 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 265 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 266 267 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 268 #endif /* CONFIG_PCI */ 269 270 #if defined(CONFIG_TSEC_ENET) 271 272 #define CONFIG_MII /* MII PHY management */ 273 #define CONFIG_TSEC1 274 #define CONFIG_TSEC1_NAME "eTSEC1" 275 #undef CONFIG_TSEC2 276 #undef CONFIG_TSEC2_NAME 277 #define CONFIG_TSEC3 278 #define CONFIG_TSEC3_NAME "eTSEC3" 279 280 #define TSEC1_PHY_ADDR 2 281 #define TSEC2_PHY_ADDR 0 282 #define TSEC3_PHY_ADDR 1 283 284 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 285 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 286 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 287 288 #define TSEC1_PHYIDX 0 289 #define TSEC2_PHYIDX 0 290 #define TSEC3_PHYIDX 0 291 292 #define CONFIG_ETHPRIME "eTSEC1" 293 294 #define CONFIG_HAS_ETH0 295 #define CONFIG_HAS_ETH1 296 #undef CONFIG_HAS_ETH2 297 #endif /* CONFIG_TSEC_ENET */ 298 299 #ifdef CONFIG_QE 300 /* QE microcode/firmware address */ 301 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 302 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 303 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 304 #endif /* CONFIG_QE */ 305 306 #ifdef CONFIG_TWR_P1025 307 /* 308 * QE UEC ethernet configuration 309 */ 310 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 311 312 #undef CONFIG_UEC_ETH 313 #define CONFIG_PHY_MODE_NEED_CHANGE 314 315 #define CONFIG_UEC_ETH1 /* ETH1 */ 316 #define CONFIG_HAS_ETH0 317 318 #ifdef CONFIG_UEC_ETH1 319 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 320 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 321 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 322 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 323 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 324 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 325 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 326 #endif /* CONFIG_UEC_ETH1 */ 327 328 #define CONFIG_UEC_ETH5 /* ETH5 */ 329 #define CONFIG_HAS_ETH1 330 331 #ifdef CONFIG_UEC_ETH5 332 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 333 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 334 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 335 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 336 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 337 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 338 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 339 #endif /* CONFIG_UEC_ETH5 */ 340 #endif /* CONFIG_TWR-P1025 */ 341 342 /* 343 * Dynamic MTD Partition support with mtdparts 344 */ 345 #define CONFIG_MTD_DEVICE 346 #define CONFIG_MTD_PARTITIONS 347 #define CONFIG_FLASH_CFI_MTD 348 349 /* 350 * Environment 351 */ 352 #ifdef CONFIG_SYS_RAMBOOT 353 #ifdef CONFIG_RAMBOOT_SDCARD 354 #define CONFIG_ENV_SIZE 0x2000 355 #define CONFIG_SYS_MMC_ENV_DEV 0 356 #else 357 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 358 #define CONFIG_ENV_SIZE 0x2000 359 #endif 360 #else 361 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 362 #define CONFIG_ENV_SIZE 0x2000 363 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 364 #endif 365 366 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 367 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 368 369 /* 370 * USB 371 */ 372 #define CONFIG_HAS_FSL_DR_USB 373 374 #if defined(CONFIG_HAS_FSL_DR_USB) 375 #ifdef CONFIG_USB_EHCI_HCD 376 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 377 #define CONFIG_USB_EHCI_FSL 378 #endif 379 #endif 380 381 #ifdef CONFIG_MMC 382 #define CONFIG_FSL_ESDHC 383 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 384 #endif 385 386 #undef CONFIG_WATCHDOG /* watchdog disabled */ 387 388 /* 389 * Miscellaneous configurable options 390 */ 391 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 392 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 393 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 394 395 /* 396 * For booting Linux, the board info and command line data 397 * have to be in the first 64 MB of memory, since this is 398 * the maximum mapped by the Linux kernel during initialization. 399 */ 400 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 401 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 402 403 /* 404 * Environment Configuration 405 */ 406 #define CONFIG_HOSTNAME unknown 407 #define CONFIG_ROOTPATH "/opt/nfsroot" 408 #define CONFIG_BOOTFILE "uImage" 409 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 410 411 /* default location for tftp and bootm */ 412 #define CONFIG_LOADADDR 1000000 413 414 #define CONFIG_EXTRA_ENV_SETTINGS \ 415 "netdev=eth0\0" \ 416 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 417 "loadaddr=1000000\0" \ 418 "bootfile=uImage\0" \ 419 "dtbfile=twr-p1025twr.dtb\0" \ 420 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 421 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 422 "tftpflash=tftpboot $loadaddr $uboot; " \ 423 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 424 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 425 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 426 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 427 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 428 "kernelflash=tftpboot $loadaddr $bootfile; " \ 429 "protect off 0xefa80000 +$filesize; " \ 430 "erase 0xefa80000 +$filesize; " \ 431 "cp.b $loadaddr 0xefa80000 $filesize; " \ 432 "protect on 0xefa80000 +$filesize; " \ 433 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 434 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 435 "protect off 0xefe80000 +$filesize; " \ 436 "erase 0xefe80000 +$filesize; " \ 437 "cp.b $loadaddr 0xefe80000 $filesize; " \ 438 "protect on 0xefe80000 +$filesize; " \ 439 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 440 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 441 "protect off 0xeeb80000 +$filesize; " \ 442 "erase 0xeeb80000 +$filesize; " \ 443 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 444 "protect on 0xeeb80000 +$filesize; " \ 445 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 446 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 447 "protect off 0xefec0000 +$filesize; " \ 448 "erase 0xefec0000 +$filesize; " \ 449 "cp.b $loadaddr 0xefec0000 $filesize; " \ 450 "protect on 0xefec0000 +$filesize; " \ 451 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 452 "consoledev=ttyS0\0" \ 453 "ramdiskaddr=2000000\0" \ 454 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 455 "fdtaddr=1e00000\0" \ 456 "bdev=sda1\0" \ 457 "norbootaddr=ef080000\0" \ 458 "norfdtaddr=ef040000\0" \ 459 "ramdisk_size=120000\0" \ 460 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 461 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 462 463 #define CONFIG_NFSBOOTCOMMAND \ 464 "setenv bootargs root=/dev/nfs rw " \ 465 "nfsroot=$serverip:$rootpath " \ 466 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 467 "console=$consoledev,$baudrate $othbootargs;" \ 468 "tftp $loadaddr $bootfile&&" \ 469 "tftp $fdtaddr $fdtfile&&" \ 470 "bootm $loadaddr - $fdtaddr" 471 472 #define CONFIG_HDBOOT \ 473 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 474 "console=$consoledev,$baudrate $othbootargs;" \ 475 "usb start;" \ 476 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 477 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 478 "bootm $loadaddr - $fdtaddr" 479 480 #define CONFIG_USB_FAT_BOOT \ 481 "setenv bootargs root=/dev/ram rw " \ 482 "console=$consoledev,$baudrate $othbootargs " \ 483 "ramdisk_size=$ramdisk_size;" \ 484 "usb start;" \ 485 "fatload usb 0:2 $loadaddr $bootfile;" \ 486 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 487 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 488 "bootm $loadaddr $ramdiskaddr $fdtaddr" 489 490 #define CONFIG_USB_EXT2_BOOT \ 491 "setenv bootargs root=/dev/ram rw " \ 492 "console=$consoledev,$baudrate $othbootargs " \ 493 "ramdisk_size=$ramdisk_size;" \ 494 "usb start;" \ 495 "ext2load usb 0:4 $loadaddr $bootfile;" \ 496 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 497 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 498 "bootm $loadaddr $ramdiskaddr $fdtaddr" 499 500 #define CONFIG_NORBOOT \ 501 "setenv bootargs root=/dev/mtdblock3 rw " \ 502 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 503 "bootm $norbootaddr - $norfdtaddr" 504 505 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 506 "setenv bootargs root=/dev/ram rw " \ 507 "console=$consoledev,$baudrate $othbootargs " \ 508 "ramdisk_size=$ramdisk_size;" \ 509 "tftp $ramdiskaddr $ramdiskfile;" \ 510 "tftp $loadaddr $bootfile;" \ 511 "tftp $fdtaddr $fdtfile;" \ 512 "bootm $loadaddr $ramdiskaddr $fdtaddr" 513 514 #define CONFIG_RAMBOOTCOMMAND \ 515 "setenv bootargs root=/dev/ram rw " \ 516 "console=$consoledev,$baudrate $othbootargs " \ 517 "ramdisk_size=$ramdisk_size;" \ 518 "bootm 0xefa80000 0xeeb80000 0xefe80000" 519 520 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 521 522 #endif /* __CONFIG_H */ 523