1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_P1020 18 #define CONFIG_VSC7385_ENET 19 #define CONFIG_SLIC 20 #define __SW_BOOT_MASK 0x03 21 #define __SW_BOOT_NOR 0xe4 22 #define __SW_BOOT_SD 0x54 23 #define CONFIG_SYS_L2_SIZE (256 << 10) 24 #endif 25 26 #if defined(CONFIG_P1020UTM) 27 #define CONFIG_BOARDNAME "P1020UTM-PC" 28 #define CONFIG_P1020 29 #define __SW_BOOT_MASK 0x03 30 #define __SW_BOOT_NOR 0xe0 31 #define __SW_BOOT_SD 0x50 32 #define CONFIG_SYS_L2_SIZE (256 << 10) 33 #endif 34 35 #if defined(CONFIG_P1020RDB_PC) 36 #define CONFIG_BOARDNAME "P1020RDB-PC" 37 #define CONFIG_NAND_FSL_ELBC 38 #define CONFIG_P1020 39 #define CONFIG_VSC7385_ENET 40 #define CONFIG_SLIC 41 #define __SW_BOOT_MASK 0x03 42 #define __SW_BOOT_NOR 0x5c 43 #define __SW_BOOT_SPI 0x1c 44 #define __SW_BOOT_SD 0x9c 45 #define __SW_BOOT_NAND 0xec 46 #define __SW_BOOT_PCIE 0x6c 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 #endif 49 50 /* 51 * P1020RDB-PD board has user selectable switches for evaluating different 52 * frequency and boot options for the P1020 device. The table that 53 * follow describe the available options. The front six binary number was in 54 * accordance with SW3[1:6]. 55 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 56 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 57 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 58 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 59 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 60 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 61 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 62 */ 63 #if defined(CONFIG_P1020RDB_PD) 64 #define CONFIG_BOARDNAME "P1020RDB-PD" 65 #define CONFIG_NAND_FSL_ELBC 66 #define CONFIG_P1020 67 #define CONFIG_VSC7385_ENET 68 #define CONFIG_SLIC 69 #define __SW_BOOT_MASK 0x03 70 #define __SW_BOOT_NOR 0x64 71 #define __SW_BOOT_SPI 0x34 72 #define __SW_BOOT_SD 0x24 73 #define __SW_BOOT_NAND 0x44 74 #define __SW_BOOT_PCIE 0x74 75 #define CONFIG_SYS_L2_SIZE (256 << 10) 76 /* 77 * Dynamic MTD Partition support with mtdparts 78 */ 79 #define CONFIG_MTD_DEVICE 80 #define CONFIG_MTD_PARTITIONS 81 #define CONFIG_CMD_MTDPARTS 82 #define CONFIG_FLASH_CFI_MTD 83 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 85 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 86 #endif 87 88 #if defined(CONFIG_P1021RDB) 89 #define CONFIG_BOARDNAME "P1021RDB-PC" 90 #define CONFIG_NAND_FSL_ELBC 91 #define CONFIG_P1021 92 #define CONFIG_QE 93 #define CONFIG_VSC7385_ENET 94 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 95 addresses in the LBC */ 96 #define __SW_BOOT_MASK 0x03 97 #define __SW_BOOT_NOR 0x5c 98 #define __SW_BOOT_SPI 0x1c 99 #define __SW_BOOT_SD 0x9c 100 #define __SW_BOOT_NAND 0xec 101 #define __SW_BOOT_PCIE 0x6c 102 #define CONFIG_SYS_L2_SIZE (256 << 10) 103 /* 104 * Dynamic MTD Partition support with mtdparts 105 */ 106 #define CONFIG_MTD_DEVICE 107 #define CONFIG_MTD_PARTITIONS 108 #define CONFIG_CMD_MTDPARTS 109 #define CONFIG_FLASH_CFI_MTD 110 #ifdef CONFIG_PHYS_64BIT 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 113 "256k(dtb),4608k(kernel),9728k(fs)," \ 114 "256k(qe-ucode-firmware),1280k(u-boot)" 115 #else 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 118 "256k(dtb),4608k(kernel),9728k(fs)," \ 119 "256k(qe-ucode-firmware),1280k(u-boot)" 120 #endif 121 #endif 122 123 #if defined(CONFIG_P1024RDB) 124 #define CONFIG_BOARDNAME "P1024RDB" 125 #define CONFIG_NAND_FSL_ELBC 126 #define CONFIG_P1024 127 #define CONFIG_SLIC 128 #define __SW_BOOT_MASK 0xf3 129 #define __SW_BOOT_NOR 0x00 130 #define __SW_BOOT_SPI 0x08 131 #define __SW_BOOT_SD 0x04 132 #define __SW_BOOT_NAND 0x0c 133 #define CONFIG_SYS_L2_SIZE (256 << 10) 134 #endif 135 136 #if defined(CONFIG_P1025RDB) 137 #define CONFIG_BOARDNAME "P1025RDB" 138 #define CONFIG_NAND_FSL_ELBC 139 #define CONFIG_P1025 140 #define CONFIG_QE 141 #define CONFIG_SLIC 142 143 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 144 addresses in the LBC */ 145 #define __SW_BOOT_MASK 0xf3 146 #define __SW_BOOT_NOR 0x00 147 #define __SW_BOOT_SPI 0x08 148 #define __SW_BOOT_SD 0x04 149 #define __SW_BOOT_NAND 0x0c 150 #define CONFIG_SYS_L2_SIZE (256 << 10) 151 #endif 152 153 #if defined(CONFIG_P2020RDB) 154 #define CONFIG_BOARDNAME "P2020RDB-PCA" 155 #define CONFIG_NAND_FSL_ELBC 156 #define CONFIG_P2020 157 #define CONFIG_VSC7385_ENET 158 #define __SW_BOOT_MASK 0x03 159 #define __SW_BOOT_NOR 0xc8 160 #define __SW_BOOT_SPI 0x28 161 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 162 #define __SW_BOOT_NAND 0xe8 163 #define __SW_BOOT_PCIE 0xa8 164 #define CONFIG_SYS_L2_SIZE (512 << 10) 165 /* 166 * Dynamic MTD Partition support with mtdparts 167 */ 168 #define CONFIG_MTD_DEVICE 169 #define CONFIG_MTD_PARTITIONS 170 #define CONFIG_CMD_MTDPARTS 171 #define CONFIG_FLASH_CFI_MTD 172 #ifdef CONFIG_PHYS_64BIT 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 175 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 176 #else 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 179 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 180 #endif 181 #endif 182 183 #ifdef CONFIG_SDCARD 184 #define CONFIG_SPL_MMC_MINIMAL 185 #define CONFIG_SPL_FLUSH_IMAGE 186 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 187 #define CONFIG_FSL_LAW /* Use common FSL init code */ 188 #define CONFIG_SYS_TEXT_BASE 0x11001000 189 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 190 #define CONFIG_SPL_PAD_TO 0x20000 191 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 192 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 193 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 194 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 195 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 196 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 197 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 198 #define CONFIG_SPL_MMC_BOOT 199 #ifdef CONFIG_SPL_BUILD 200 #define CONFIG_SPL_COMMON_INIT_DDR 201 #endif 202 #endif 203 204 #ifdef CONFIG_SPIFLASH 205 #define CONFIG_SPL_SPI_SUPPORT 206 #define CONFIG_SPL_SPI_FLASH_SUPPORT 207 #define CONFIG_SPL_SPI_FLASH_MINIMAL 208 #define CONFIG_SPL_FLUSH_IMAGE 209 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 210 #define CONFIG_FSL_LAW /* Use common FSL init code */ 211 #define CONFIG_SYS_TEXT_BASE 0x11001000 212 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 213 #define CONFIG_SPL_PAD_TO 0x20000 214 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 215 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 216 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 217 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 218 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 219 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 220 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 221 #define CONFIG_SPL_SPI_BOOT 222 #ifdef CONFIG_SPL_BUILD 223 #define CONFIG_SPL_COMMON_INIT_DDR 224 #endif 225 #endif 226 227 #ifdef CONFIG_NAND 228 #ifdef CONFIG_TPL_BUILD 229 #define CONFIG_SPL_NAND_BOOT 230 #define CONFIG_SPL_FLUSH_IMAGE 231 #define CONFIG_SPL_NAND_INIT 232 #define CONFIG_SPL_COMMON_INIT_DDR 233 #define CONFIG_SPL_MAX_SIZE (128 << 10) 234 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 235 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 236 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 237 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 238 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 240 #elif defined(CONFIG_SPL_BUILD) 241 #define CONFIG_SPL_INIT_MINIMAL 242 #define CONFIG_SPL_FLUSH_IMAGE 243 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 244 #define CONFIG_SPL_TEXT_BASE 0xff800000 245 #define CONFIG_SPL_MAX_SIZE 4096 246 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 247 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 248 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 249 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 250 #endif /* not CONFIG_TPL_BUILD */ 251 252 #define CONFIG_SPL_PAD_TO 0x20000 253 #define CONFIG_TPL_PAD_TO 0x20000 254 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 255 #define CONFIG_SYS_TEXT_BASE 0x11001000 256 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 257 #endif 258 259 #ifndef CONFIG_SYS_TEXT_BASE 260 #define CONFIG_SYS_TEXT_BASE 0xeff40000 261 #endif 262 263 #ifndef CONFIG_RESET_VECTOR_ADDRESS 264 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 265 #endif 266 267 #ifndef CONFIG_SYS_MONITOR_BASE 268 #ifdef CONFIG_SPL_BUILD 269 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 270 #else 271 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 272 #endif 273 #endif 274 275 /* High Level Configuration Options */ 276 #define CONFIG_BOOKE 277 #define CONFIG_E500 278 279 #define CONFIG_MP 280 281 #define CONFIG_FSL_ELBC 282 #define CONFIG_PCI 283 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 284 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 285 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 286 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 287 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 288 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 289 290 #define CONFIG_FSL_LAW 291 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 292 #define CONFIG_ENV_OVERWRITE 293 294 #define CONFIG_CMD_SATA 295 #define CONFIG_SATA_SIL 296 #define CONFIG_SYS_SATA_MAX_DEVICE 2 297 #define CONFIG_LIBATA 298 #define CONFIG_LBA48 299 300 #if defined(CONFIG_P2020RDB) 301 #define CONFIG_SYS_CLK_FREQ 100000000 302 #else 303 #define CONFIG_SYS_CLK_FREQ 66666666 304 #endif 305 #define CONFIG_DDR_CLK_FREQ 66666666 306 307 #define CONFIG_HWCONFIG 308 /* 309 * These can be toggled for performance analysis, otherwise use default. 310 */ 311 #define CONFIG_L2_CACHE 312 #define CONFIG_BTB 313 314 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 315 316 #define CONFIG_ENABLE_36BIT_PHYS 317 318 #ifdef CONFIG_PHYS_64BIT 319 #define CONFIG_ADDR_MAP 1 320 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 321 #endif 322 323 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 324 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 325 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 326 327 #define CONFIG_SYS_CCSRBAR 0xffe00000 328 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 329 330 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 331 SPL code*/ 332 #ifdef CONFIG_SPL_BUILD 333 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 334 #endif 335 336 /* DDR Setup */ 337 #define CONFIG_SYS_FSL_DDR3 338 #define CONFIG_SYS_DDR_RAW_TIMING 339 #define CONFIG_DDR_SPD 340 #define CONFIG_SYS_SPD_BUS_NUM 1 341 #define SPD_EEPROM_ADDRESS 0x52 342 #undef CONFIG_FSL_DDR_INTERACTIVE 343 344 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 345 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 346 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 347 #else 348 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 349 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 350 #endif 351 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 352 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 353 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 354 355 #define CONFIG_NUM_DDR_CONTROLLERS 1 356 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 357 358 /* Default settings for DDR3 */ 359 #ifndef CONFIG_P2020RDB 360 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 361 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 362 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 363 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 364 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 365 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 366 367 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 368 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 369 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 370 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 371 372 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 373 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 374 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 375 #define CONFIG_SYS_DDR_RCW_1 0x00000000 376 #define CONFIG_SYS_DDR_RCW_2 0x00000000 377 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 378 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 379 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 380 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 381 382 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 383 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 384 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 385 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 386 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 387 #define CONFIG_SYS_DDR_MODE_1 0x40461520 388 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 389 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 390 #endif 391 392 #undef CONFIG_CLOCKS_IN_MHZ 393 394 /* 395 * Memory map 396 * 397 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 398 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 399 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 400 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 401 * (early boot only) 402 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 403 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 404 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 405 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 406 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 407 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 408 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 409 */ 410 411 /* 412 * Local Bus Definitions 413 */ 414 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) 415 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 416 #define CONFIG_SYS_FLASH_BASE 0xec000000 417 #elif defined(CONFIG_P1020UTM) 418 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 419 #define CONFIG_SYS_FLASH_BASE 0xee000000 420 #else 421 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 422 #define CONFIG_SYS_FLASH_BASE 0xef000000 423 #endif 424 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 427 #else 428 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 429 #endif 430 431 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 432 | BR_PS_16 | BR_V) 433 434 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 435 436 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 437 #define CONFIG_SYS_FLASH_QUIET_TEST 438 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 439 440 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 441 442 #undef CONFIG_SYS_FLASH_CHECKSUM 443 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 444 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 445 446 #define CONFIG_FLASH_CFI_DRIVER 447 #define CONFIG_SYS_FLASH_CFI 448 #define CONFIG_SYS_FLASH_EMPTY_INFO 449 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 450 451 /* Nand Flash */ 452 #ifdef CONFIG_NAND_FSL_ELBC 453 #define CONFIG_SYS_NAND_BASE 0xff800000 454 #ifdef CONFIG_PHYS_64BIT 455 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 456 #else 457 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 458 #endif 459 460 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 461 #define CONFIG_SYS_MAX_NAND_DEVICE 1 462 #define CONFIG_CMD_NAND 463 #if defined(CONFIG_P1020RDB_PD) 464 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 465 #else 466 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 467 #endif 468 469 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 470 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 471 | BR_PS_8 /* Port Size = 8 bit */ \ 472 | BR_MS_FCM /* MSEL = FCM */ \ 473 | BR_V) /* valid */ 474 #if defined(CONFIG_P1020RDB_PD) 475 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 476 | OR_FCM_PGS /* Large Page*/ \ 477 | OR_FCM_CSCT \ 478 | OR_FCM_CST \ 479 | OR_FCM_CHT \ 480 | OR_FCM_SCY_1 \ 481 | OR_FCM_TRLX \ 482 | OR_FCM_EHTR) 483 #else 484 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 485 | OR_FCM_CSCT \ 486 | OR_FCM_CST \ 487 | OR_FCM_CHT \ 488 | OR_FCM_SCY_1 \ 489 | OR_FCM_TRLX \ 490 | OR_FCM_EHTR) 491 #endif 492 #endif /* CONFIG_NAND_FSL_ELBC */ 493 494 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 495 496 #define CONFIG_SYS_INIT_RAM_LOCK 497 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 498 #ifdef CONFIG_PHYS_64BIT 499 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 500 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 501 /* The assembler doesn't like typecast */ 502 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 503 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 504 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 505 #else 506 /* Initial L1 address */ 507 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 508 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 509 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 510 #endif 511 /* Size of used area in RAM */ 512 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 513 514 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 515 GENERATED_GBL_DATA_SIZE) 516 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 517 518 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 519 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 520 521 #define CONFIG_SYS_CPLD_BASE 0xffa00000 522 #ifdef CONFIG_PHYS_64BIT 523 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 524 #else 525 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 526 #endif 527 /* CPLD config size: 1Mb */ 528 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 529 BR_PS_8 | BR_V) 530 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 531 532 #define CONFIG_SYS_PMC_BASE 0xff980000 533 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 534 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 535 BR_PS_8 | BR_V) 536 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 537 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 538 OR_GPCM_EAD) 539 540 #ifdef CONFIG_NAND 541 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 542 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 543 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 544 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 545 #else 546 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 547 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 548 #ifdef CONFIG_NAND_FSL_ELBC 549 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 550 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 551 #endif 552 #endif 553 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 554 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 555 556 /* Vsc7385 switch */ 557 #ifdef CONFIG_VSC7385_ENET 558 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 559 560 #ifdef CONFIG_PHYS_64BIT 561 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 562 #else 563 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 564 #endif 565 566 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 567 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 568 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 569 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 570 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 571 572 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 573 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 574 575 /* The size of the VSC7385 firmware image */ 576 #define CONFIG_VSC7385_IMAGE_SIZE 8192 577 #endif 578 579 /* 580 * Config the L2 Cache as L2 SRAM 581 */ 582 #if defined(CONFIG_SPL_BUILD) 583 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 584 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 585 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 586 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 587 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 588 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 589 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 590 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 591 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 592 #if defined(CONFIG_P2020RDB) 593 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 594 #else 595 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 596 #endif 597 #elif defined(CONFIG_NAND) 598 #ifdef CONFIG_TPL_BUILD 599 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 600 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 601 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 602 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 603 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 604 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 605 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 606 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 607 #else 608 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 609 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 610 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 611 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 612 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 613 #endif /* CONFIG_TPL_BUILD */ 614 #endif 615 #endif 616 617 /* Serial Port - controlled on board with jumper J8 618 * open - index 2 619 * shorted - index 1 620 */ 621 #define CONFIG_CONS_INDEX 1 622 #undef CONFIG_SERIAL_SOFTWARE_FIFO 623 #define CONFIG_SYS_NS16550_SERIAL 624 #define CONFIG_SYS_NS16550_REG_SIZE 1 625 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 626 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 627 #define CONFIG_NS16550_MIN_FUNCTIONS 628 #endif 629 630 #define CONFIG_SYS_BAUDRATE_TABLE \ 631 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 632 633 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 634 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 635 636 /* I2C */ 637 #define CONFIG_SYS_I2C 638 #define CONFIG_SYS_I2C_FSL 639 #define CONFIG_SYS_FSL_I2C_SPEED 400000 640 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 641 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 642 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 643 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 644 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 645 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 646 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 647 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 648 649 /* 650 * I2C2 EEPROM 651 */ 652 #undef CONFIG_ID_EEPROM 653 654 #define CONFIG_RTC_PT7C4338 655 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 656 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 657 658 /* enable read and write access to EEPROM */ 659 #define CONFIG_CMD_EEPROM 660 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 661 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 662 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 663 664 /* 665 * eSPI - Enhanced SPI 666 */ 667 #define CONFIG_HARD_SPI 668 669 #if defined(CONFIG_SPI_FLASH) 670 #define CONFIG_SF_DEFAULT_SPEED 10000000 671 #define CONFIG_SF_DEFAULT_MODE 0 672 #endif 673 674 #if defined(CONFIG_PCI) 675 /* 676 * General PCI 677 * Memory space is mapped 1-1, but I/O space must start from 0. 678 */ 679 680 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 681 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 682 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 683 #ifdef CONFIG_PHYS_64BIT 684 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 685 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 686 #else 687 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 688 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 689 #endif 690 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 691 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 692 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 693 #ifdef CONFIG_PHYS_64BIT 694 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 695 #else 696 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 697 #endif 698 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 699 700 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 701 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 702 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 703 #ifdef CONFIG_PHYS_64BIT 704 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 705 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 706 #else 707 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 708 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 709 #endif 710 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 711 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 712 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 713 #ifdef CONFIG_PHYS_64BIT 714 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 715 #else 716 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 717 #endif 718 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 719 720 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 721 #define CONFIG_CMD_PCI 722 723 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 724 #define CONFIG_DOS_PARTITION 725 #endif /* CONFIG_PCI */ 726 727 #if defined(CONFIG_TSEC_ENET) 728 #define CONFIG_MII /* MII PHY management */ 729 #define CONFIG_TSEC1 730 #define CONFIG_TSEC1_NAME "eTSEC1" 731 #define CONFIG_TSEC2 732 #define CONFIG_TSEC2_NAME "eTSEC2" 733 #define CONFIG_TSEC3 734 #define CONFIG_TSEC3_NAME "eTSEC3" 735 736 #define TSEC1_PHY_ADDR 2 737 #define TSEC2_PHY_ADDR 0 738 #define TSEC3_PHY_ADDR 1 739 740 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 741 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 742 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 743 744 #define TSEC1_PHYIDX 0 745 #define TSEC2_PHYIDX 0 746 #define TSEC3_PHYIDX 0 747 748 #define CONFIG_ETHPRIME "eTSEC1" 749 750 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 751 752 #define CONFIG_HAS_ETH0 753 #define CONFIG_HAS_ETH1 754 #define CONFIG_HAS_ETH2 755 #endif /* CONFIG_TSEC_ENET */ 756 757 #ifdef CONFIG_QE 758 /* QE microcode/firmware address */ 759 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 760 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 761 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 762 #endif /* CONFIG_QE */ 763 764 #ifdef CONFIG_P1025RDB 765 /* 766 * QE UEC ethernet configuration 767 */ 768 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 769 770 #undef CONFIG_UEC_ETH 771 #define CONFIG_PHY_MODE_NEED_CHANGE 772 773 #define CONFIG_UEC_ETH1 /* ETH1 */ 774 #define CONFIG_HAS_ETH0 775 776 #ifdef CONFIG_UEC_ETH1 777 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 778 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 779 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 780 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 781 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 782 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 783 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 784 #endif /* CONFIG_UEC_ETH1 */ 785 786 #define CONFIG_UEC_ETH5 /* ETH5 */ 787 #define CONFIG_HAS_ETH1 788 789 #ifdef CONFIG_UEC_ETH5 790 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 791 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 792 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 793 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 794 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 795 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 796 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 797 #endif /* CONFIG_UEC_ETH5 */ 798 #endif /* CONFIG_P1025RDB */ 799 800 /* 801 * Environment 802 */ 803 #ifdef CONFIG_SPIFLASH 804 #define CONFIG_ENV_IS_IN_SPI_FLASH 805 #define CONFIG_ENV_SPI_BUS 0 806 #define CONFIG_ENV_SPI_CS 0 807 #define CONFIG_ENV_SPI_MAX_HZ 10000000 808 #define CONFIG_ENV_SPI_MODE 0 809 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 810 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 811 #define CONFIG_ENV_SECT_SIZE 0x10000 812 #elif defined(CONFIG_SDCARD) 813 #define CONFIG_ENV_IS_IN_MMC 814 #define CONFIG_FSL_FIXED_MMC_LOCATION 815 #define CONFIG_ENV_SIZE 0x2000 816 #define CONFIG_SYS_MMC_ENV_DEV 0 817 #elif defined(CONFIG_NAND) 818 #ifdef CONFIG_TPL_BUILD 819 #define CONFIG_ENV_SIZE 0x2000 820 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 821 #else 822 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 823 #endif 824 #define CONFIG_ENV_IS_IN_NAND 825 #define CONFIG_ENV_OFFSET (1024 * 1024) 826 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 827 #elif defined(CONFIG_SYS_RAMBOOT) 828 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 829 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 830 #define CONFIG_ENV_SIZE 0x2000 831 #else 832 #define CONFIG_ENV_IS_IN_FLASH 833 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 834 #define CONFIG_ENV_SIZE 0x2000 835 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 836 #endif 837 838 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 839 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 840 841 /* 842 * Command line configuration. 843 */ 844 #define CONFIG_CMD_IRQ 845 #define CONFIG_CMD_DATE 846 #define CONFIG_CMD_REGINFO 847 848 /* 849 * USB 850 */ 851 #define CONFIG_HAS_FSL_DR_USB 852 853 #if defined(CONFIG_HAS_FSL_DR_USB) 854 #define CONFIG_USB_EHCI 855 856 #ifdef CONFIG_USB_EHCI 857 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 858 #define CONFIG_USB_EHCI_FSL 859 #endif 860 #endif 861 862 #if defined(CONFIG_P1020RDB_PD) 863 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 864 #endif 865 866 #define CONFIG_MMC 867 868 #ifdef CONFIG_MMC 869 #define CONFIG_FSL_ESDHC 870 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 871 #define CONFIG_GENERIC_MMC 872 #endif 873 874 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 875 || defined(CONFIG_FSL_SATA) 876 #define CONFIG_DOS_PARTITION 877 #endif 878 879 #undef CONFIG_WATCHDOG /* watchdog disabled */ 880 881 /* 882 * Miscellaneous configurable options 883 */ 884 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 885 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 886 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 887 #if defined(CONFIG_CMD_KGDB) 888 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 889 #else 890 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 891 #endif 892 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 893 /* Print Buffer Size */ 894 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 895 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 896 897 /* 898 * For booting Linux, the board info and command line data 899 * have to be in the first 64 MB of memory, since this is 900 * the maximum mapped by the Linux kernel during initialization. 901 */ 902 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 903 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 904 905 #if defined(CONFIG_CMD_KGDB) 906 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 907 #endif 908 909 /* 910 * Environment Configuration 911 */ 912 #define CONFIG_HOSTNAME unknown 913 #define CONFIG_ROOTPATH "/opt/nfsroot" 914 #define CONFIG_BOOTFILE "uImage" 915 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 916 917 /* default location for tftp and bootm */ 918 #define CONFIG_LOADADDR 1000000 919 920 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 921 922 #define CONFIG_BAUDRATE 115200 923 924 #ifdef __SW_BOOT_NOR 925 #define __NOR_RST_CMD \ 926 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 927 i2c mw 18 3 __SW_BOOT_MASK 1; reset 928 #endif 929 #ifdef __SW_BOOT_SPI 930 #define __SPI_RST_CMD \ 931 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 932 i2c mw 18 3 __SW_BOOT_MASK 1; reset 933 #endif 934 #ifdef __SW_BOOT_SD 935 #define __SD_RST_CMD \ 936 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 937 i2c mw 18 3 __SW_BOOT_MASK 1; reset 938 #endif 939 #ifdef __SW_BOOT_NAND 940 #define __NAND_RST_CMD \ 941 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 942 i2c mw 18 3 __SW_BOOT_MASK 1; reset 943 #endif 944 #ifdef __SW_BOOT_PCIE 945 #define __PCIE_RST_CMD \ 946 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 947 i2c mw 18 3 __SW_BOOT_MASK 1; reset 948 #endif 949 950 #define CONFIG_EXTRA_ENV_SETTINGS \ 951 "netdev=eth0\0" \ 952 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 953 "loadaddr=1000000\0" \ 954 "bootfile=uImage\0" \ 955 "tftpflash=tftpboot $loadaddr $uboot; " \ 956 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 957 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 958 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 959 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 960 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 961 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 962 "consoledev=ttyS0\0" \ 963 "ramdiskaddr=2000000\0" \ 964 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 965 "fdtaddr=1e00000\0" \ 966 "bdev=sda1\0" \ 967 "jffs2nor=mtdblock3\0" \ 968 "norbootaddr=ef080000\0" \ 969 "norfdtaddr=ef040000\0" \ 970 "jffs2nand=mtdblock9\0" \ 971 "nandbootaddr=100000\0" \ 972 "nandfdtaddr=80000\0" \ 973 "ramdisk_size=120000\0" \ 974 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 975 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 976 __stringify(__NOR_RST_CMD)"\0" \ 977 __stringify(__SPI_RST_CMD)"\0" \ 978 __stringify(__SD_RST_CMD)"\0" \ 979 __stringify(__NAND_RST_CMD)"\0" \ 980 __stringify(__PCIE_RST_CMD)"\0" 981 982 #define CONFIG_NFSBOOTCOMMAND \ 983 "setenv bootargs root=/dev/nfs rw " \ 984 "nfsroot=$serverip:$rootpath " \ 985 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 986 "console=$consoledev,$baudrate $othbootargs;" \ 987 "tftp $loadaddr $bootfile;" \ 988 "tftp $fdtaddr $fdtfile;" \ 989 "bootm $loadaddr - $fdtaddr" 990 991 #define CONFIG_HDBOOT \ 992 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 993 "console=$consoledev,$baudrate $othbootargs;" \ 994 "usb start;" \ 995 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 996 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 997 "bootm $loadaddr - $fdtaddr" 998 999 #define CONFIG_USB_FAT_BOOT \ 1000 "setenv bootargs root=/dev/ram rw " \ 1001 "console=$consoledev,$baudrate $othbootargs " \ 1002 "ramdisk_size=$ramdisk_size;" \ 1003 "usb start;" \ 1004 "fatload usb 0:2 $loadaddr $bootfile;" \ 1005 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 1006 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 1007 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1008 1009 #define CONFIG_USB_EXT2_BOOT \ 1010 "setenv bootargs root=/dev/ram rw " \ 1011 "console=$consoledev,$baudrate $othbootargs " \ 1012 "ramdisk_size=$ramdisk_size;" \ 1013 "usb start;" \ 1014 "ext2load usb 0:4 $loadaddr $bootfile;" \ 1015 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 1016 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 1017 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1018 1019 #define CONFIG_NORBOOT \ 1020 "setenv bootargs root=/dev/$jffs2nor rw " \ 1021 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 1022 "bootm $norbootaddr - $norfdtaddr" 1023 1024 #define CONFIG_RAMBOOTCOMMAND \ 1025 "setenv bootargs root=/dev/ram rw " \ 1026 "console=$consoledev,$baudrate $othbootargs " \ 1027 "ramdisk_size=$ramdisk_size;" \ 1028 "tftp $ramdiskaddr $ramdiskfile;" \ 1029 "tftp $loadaddr $bootfile;" \ 1030 "tftp $fdtaddr $fdtfile;" \ 1031 "bootm $loadaddr $ramdiskaddr $fdtaddr" 1032 1033 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 1034 1035 #endif /* __CONFIG_H */ 1036