1 /* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ 27 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 28 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 29 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 30 #define CONFIG_OMAP3_OVERO 1 /* working with overo */ 31 32 #define CONFIG_SDRC /* The chip has SDRC controller */ 33 34 #include <asm/arch/cpu.h> /* get chip and board defs */ 35 #include <asm/arch/omap3.h> 36 37 /* 38 * Display CPU and Board information 39 */ 40 #define CONFIG_DISPLAY_CPUINFO 1 41 #define CONFIG_DISPLAY_BOARDINFO 1 42 43 /* Clock Defines */ 44 #define V_OSCK 26000000 /* Clock output from T2 */ 45 #define V_SCLK (V_OSCK >> 1) 46 47 #undef CONFIG_USE_IRQ /* no support for IRQs */ 48 #define CONFIG_MISC_INIT_R 49 50 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 51 #define CONFIG_SETUP_MEMORY_TAGS 1 52 #define CONFIG_INITRD_TAG 1 53 #define CONFIG_REVISION_TAG 1 54 55 #define CONFIG_OF_LIBFDT 1 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 61 /* Sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 63 /* initial data */ 64 65 /* 66 * Hardware drivers 67 */ 68 69 /* 70 * NS16550 Configuration 71 */ 72 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 73 74 #define CONFIG_SYS_NS16550 75 #define CONFIG_SYS_NS16550_SERIAL 76 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 77 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 78 79 /* 80 * select serial console configuration 81 */ 82 #define CONFIG_CONS_INDEX 3 83 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 84 #define CONFIG_SERIAL3 3 85 86 /* allow to overwrite serial and ethaddr */ 87 #define CONFIG_ENV_OVERWRITE 88 #define CONFIG_BAUDRATE 115200 89 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 90 115200} 91 #define CONFIG_GENERIC_MMC 1 92 #define CONFIG_MMC 1 93 #define CONFIG_OMAP_HSMMC 1 94 #define CONFIG_DOS_PARTITION 1 95 96 /* DDR - I use Micron DDR */ 97 #define CONFIG_OMAP3_MICRON_DDR 1 98 99 /* commands to include */ 100 #include <config_cmd_default.h> 101 102 #define CONFIG_CMD_CACHE 103 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 104 #define CONFIG_CMD_FAT /* FAT support */ 105 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 106 107 #define CONFIG_CMD_I2C /* I2C serial bus support */ 108 #define CONFIG_CMD_MMC /* MMC support */ 109 #define CONFIG_CMD_NAND /* NAND support */ 110 111 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 112 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 113 #undef CONFIG_CMD_IMI /* iminfo */ 114 #undef CONFIG_CMD_IMLS /* List all found images */ 115 #undef CONFIG_CMD_NFS /* NFS support */ 116 #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 117 118 #define CONFIG_SYS_NO_FLASH 119 #define CONFIG_HARD_I2C 1 120 #define CONFIG_SYS_I2C_SPEED 100000 121 #define CONFIG_SYS_I2C_SLAVE 1 122 #define CONFIG_SYS_I2C_BUS 0 123 #define CONFIG_SYS_I2C_BUS_SELECT 1 124 #define CONFIG_I2C_MULTI_BUS 1 125 #define CONFIG_DRIVER_OMAP34XX_I2C 1 126 127 /* 128 * TWL4030 129 */ 130 #define CONFIG_TWL4030_POWER 1 131 #define CONFIG_TWL4030_LED 1 132 133 /* 134 * Board NAND Info. 135 */ 136 #define CONFIG_SYS_NAND_QUIET_TEST 1 137 #define CONFIG_NAND_OMAP_GPMC 138 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 139 /* to access nand */ 140 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 141 /* to access nand */ 142 /* at CS0 */ 143 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 144 145 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 146 /* devices */ 147 #define CONFIG_JFFS2_NAND 148 /* nand device jffs2 lives on */ 149 #define CONFIG_JFFS2_DEV "nand0" 150 /* start of jffs2 partition */ 151 #define CONFIG_JFFS2_PART_OFFSET 0x680000 152 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 153 /* partition */ 154 155 /* Environment information */ 156 #define CONFIG_BOOTDELAY 5 157 158 #define CONFIG_EXTRA_ENV_SETTINGS \ 159 "loadaddr=0x82000000\0" \ 160 "console=ttyS2,115200n8\0" \ 161 "mpurate=500\0" \ 162 "vram=12M\0" \ 163 "dvimode=1024x768MR-16@60\0" \ 164 "defaultdisplay=dvi\0" \ 165 "mmcdev=0\0" \ 166 "mmcroot=/dev/mmcblk0p2 rw\0" \ 167 "mmcrootfstype=ext3 rootwait\0" \ 168 "nandroot=/dev/mtdblock4 rw\0" \ 169 "nandrootfstype=jffs2\0" \ 170 "mmcargs=setenv bootargs console=${console} " \ 171 "mpurate=${mpurate} " \ 172 "vram=${vram} " \ 173 "omapfb.mode=dvi:${dvimode} " \ 174 "omapfb.debug=y " \ 175 "omapdss.def_disp=${defaultdisplay} " \ 176 "root=${mmcroot} " \ 177 "rootfstype=${mmcrootfstype}\0" \ 178 "nandargs=setenv bootargs console=${console} " \ 179 "mpurate=${mpurate} " \ 180 "vram=${vram} " \ 181 "omapfb.mode=dvi:${dvimode} " \ 182 "omapfb.debug=y " \ 183 "omapdss.def_disp=${defaultdisplay} " \ 184 "root=${nandroot} " \ 185 "rootfstype=${nandrootfstype}\0" \ 186 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 187 "bootscript=echo Running bootscript from mmc ...; " \ 188 "source ${loadaddr}\0" \ 189 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 190 "mmcboot=echo Booting from mmc ...; " \ 191 "run mmcargs; " \ 192 "bootm ${loadaddr}\0" \ 193 "nandboot=echo Booting from nand ...; " \ 194 "run nandargs; " \ 195 "nand read ${loadaddr} 280000 400000; " \ 196 "bootm ${loadaddr}\0" \ 197 198 #define CONFIG_BOOTCOMMAND \ 199 "if mmc rescan ${mmcdev}; then " \ 200 "if run loadbootscript; then " \ 201 "run bootscript; " \ 202 "else " \ 203 "if run loaduimage; then " \ 204 "run mmcboot; " \ 205 "else run nandboot; " \ 206 "fi; " \ 207 "fi; " \ 208 "else run nandboot; fi" 209 210 #define CONFIG_AUTO_COMPLETE 1 211 /* 212 * Miscellaneous configurable options 213 */ 214 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 215 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 216 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 217 #define CONFIG_SYS_PROMPT "Overo # " 218 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 219 /* Print Buffer Size */ 220 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 221 sizeof(CONFIG_SYS_PROMPT) + 16) 222 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 223 /* args */ 224 /* Boot Argument Buffer Size */ 225 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 226 /* memtest works on */ 227 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 228 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 229 0x01F00000) /* 31MB */ 230 231 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 232 /* address */ 233 /* 234 * OMAP3 has 12 GP timers, they can be driven by the system clock 235 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 236 * This rate is divided by a local divisor. 237 */ 238 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 239 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 240 #define CONFIG_SYS_HZ 1000 241 242 /*----------------------------------------------------------------------- 243 * Stack sizes 244 * 245 * The stack sizes are set up in start.S using the settings below 246 */ 247 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 248 #ifdef CONFIG_USE_IRQ 249 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 250 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 251 #endif 252 253 /*----------------------------------------------------------------------- 254 * Physical Memory Map 255 */ 256 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 257 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 258 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 259 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 260 261 /* SDRAM Bank Allocation method */ 262 #define SDRC_R_B_C 1 263 264 /*----------------------------------------------------------------------- 265 * FLASH and environment organization 266 */ 267 268 /* **** PISMO SUPPORT *** */ 269 270 /* Configure the PISMO */ 271 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 272 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 273 274 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 275 276 #if defined(CONFIG_CMD_NAND) 277 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 278 #endif 279 280 /* Monitor at start of flash */ 281 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 282 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 283 284 #define CONFIG_ENV_IS_IN_NAND 1 285 #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 286 #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 287 288 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 289 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 290 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 291 292 #if defined(CONFIG_CMD_NET) 293 /*---------------------------------------------------------------------------- 294 * SMSC9211 Ethernet from SMSC9118 family 295 *---------------------------------------------------------------------------- 296 */ 297 298 #define CONFIG_NET_MULTI 299 #define CONFIG_SMC911X 1 300 #define CONFIG_SMC911X_32_BIT 301 #define CONFIG_SMC911X_BASE 0x2C000000 302 303 #endif /* (CONFIG_CMD_NET) */ 304 305 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 306 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 307 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 308 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 309 CONFIG_SYS_INIT_RAM_SIZE - \ 310 GENERATED_GBL_DATA_SIZE) 311 312 #endif /* __CONFIG_H */ 313