183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2633fa0e7SStefan Roese /* 3633fa0e7SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4633fa0e7SStefan Roese */ 5633fa0e7SStefan Roese 6633fa0e7SStefan Roese #ifndef _CONFIG_MVEBU_ARMADA_8K_H 7633fa0e7SStefan Roese #define _CONFIG_MVEBU_ARMADA_8K_H 8633fa0e7SStefan Roese 9633fa0e7SStefan Roese /* 10633fa0e7SStefan Roese * High Level Configuration Options (easy to change) 11633fa0e7SStefan Roese */ 12633fa0e7SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 13633fa0e7SStefan Roese 14633fa0e7SStefan Roese /* additions for new ARM relocation support */ 15633fa0e7SStefan Roese #define CONFIG_SYS_SDRAM_BASE 0x00000000 16633fa0e7SStefan Roese 17633fa0e7SStefan Roese /* auto boot */ 18633fa0e7SStefan Roese #define CONFIG_PREBOOT 19633fa0e7SStefan Roese 20633fa0e7SStefan Roese #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 21633fa0e7SStefan Roese 115200, 230400, 460800, 921600 } 22633fa0e7SStefan Roese 23633fa0e7SStefan Roese /* 24633fa0e7SStefan Roese * For booting Linux, the board info and command line data 25633fa0e7SStefan Roese * have to be in the first 8 MB of memory, since this is 26633fa0e7SStefan Roese * the maximum mapped by the Linux kernel during initialization. 27633fa0e7SStefan Roese */ 28633fa0e7SStefan Roese #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 29633fa0e7SStefan Roese #define CONFIG_INITRD_TAG /* enable INITRD tag */ 30633fa0e7SStefan Roese #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ 31633fa0e7SStefan Roese 32633fa0e7SStefan Roese #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 33633fa0e7SStefan Roese 34633fa0e7SStefan Roese /* 35633fa0e7SStefan Roese * Size of malloc() pool 36633fa0e7SStefan Roese */ 37633fa0e7SStefan Roese #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ 38633fa0e7SStefan Roese 39633fa0e7SStefan Roese /* 40633fa0e7SStefan Roese * Other required minimal configurations 41633fa0e7SStefan Roese */ 42633fa0e7SStefan Roese #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 43633fa0e7SStefan Roese #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ 44633fa0e7SStefan Roese #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ 45633fa0e7SStefan Roese #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ 46633fa0e7SStefan Roese #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 47633fa0e7SStefan Roese #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 48633fa0e7SStefan Roese 49633fa0e7SStefan Roese /* End of 16M scrubbed by training in bootrom */ 50633fa0e7SStefan Roese #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) 51633fa0e7SStefan Roese 52633fa0e7SStefan Roese /* 53633fa0e7SStefan Roese * SPI Flash configuration 54633fa0e7SStefan Roese */ 55633fa0e7SStefan Roese 56633fa0e7SStefan Roese #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ 57633fa0e7SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 58633fa0e7SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 59633fa0e7SStefan Roese 60*7e1d3220SBaruch Siach /* When runtime detection fails this is the default */ 61*7e1d3220SBaruch Siach #define CONFIG_SYS_MMC_ENV_DEV 0 62*7e1d3220SBaruch Siach 63f59472e8SKonstantin Porotchkin #define CONFIG_SYS_MAX_NAND_DEVICE 1 64f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_MAX_CHIPS 1 65f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_ONFI_DETECTION 66f59472e8SKonstantin Porotchkin #define CONFIG_SYS_NAND_USE_FLASH_BBT 67f59472e8SKonstantin Porotchkin 68def84429SStefan Roese /* 69def84429SStefan Roese * Ethernet Driver configuration 70def84429SStefan Roese */ 71def84429SStefan Roese #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 72def84429SStefan Roese #define CONFIG_ARP_TIMEOUT 200 73def84429SStefan Roese #define CONFIG_NET_RETRY_COUNT 50 74def84429SStefan Roese 75cbb89ed0SBin Meng #define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) 76633fa0e7SStefan Roese 77633fa0e7SStefan Roese /* USB ethernet */ 78633fa0e7SStefan Roese 79633fa0e7SStefan Roese /* 80633fa0e7SStefan Roese * SATA/SCSI/AHCI configuration 81633fa0e7SStefan Roese */ 82633fa0e7SStefan Roese #define CONFIG_SCSI_AHCI_PLAT 83633fa0e7SStefan Roese #define CONFIG_LBA48 84633fa0e7SStefan Roese #define CONFIG_SYS_64BIT_LBA 85633fa0e7SStefan Roese 86633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 87633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_LUN 1 88633fa0e7SStefan Roese #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 89633fa0e7SStefan Roese CONFIG_SYS_SCSI_MAX_LUN) 90633fa0e7SStefan Roese 911ec5aa63SStefan Roese /* 921ec5aa63SStefan Roese * PCI configuration 931ec5aa63SStefan Roese */ 941ec5aa63SStefan Roese #ifdef CONFIG_PCIE_DW_MVEBU 951ec5aa63SStefan Roese #define CONFIG_E1000 961ec5aa63SStefan Roese #endif 971ec5aa63SStefan Roese 98bdca661eSMark Kettenis #define BOOT_TARGET_DEVICES(func) \ 99bdca661eSMark Kettenis func(MMC, mmc, 1) \ 100bdca661eSMark Kettenis func(MMC, mmc, 0) \ 101bdca661eSMark Kettenis func(USB, usb, 0) \ 102bdca661eSMark Kettenis func(SCSI, scsi, 0) \ 103bdca661eSMark Kettenis func(PXE, pxe, na) \ 104bdca661eSMark Kettenis func(DHCP, dhcp, na) 105bdca661eSMark Kettenis 106bdca661eSMark Kettenis #include <config_distro_bootcmd.h> 107bdca661eSMark Kettenis 108bdca661eSMark Kettenis #define CONFIG_EXTRA_ENV_SETTINGS \ 109bdca661eSMark Kettenis "scriptaddr=0x4d00000\0" \ 110bdca661eSMark Kettenis "pxefile_addr_r=0x4e00000\0" \ 111bdca661eSMark Kettenis "fdt_addr_r=0x4f00000\0" \ 112bdca661eSMark Kettenis "kernel_addr_r=0x5000000\0" \ 113bdca661eSMark Kettenis "ramdisk_addr_r=0x8000000\0" \ 114bdca661eSMark Kettenis "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ 115bdca661eSMark Kettenis BOOTENV 116bdca661eSMark Kettenis 117633fa0e7SStefan Roese #endif /* _CONFIG_MVEBU_ARMADA_8K_H */ 118