16c0bbdccSNobuhiro Iwamatsu /* 26c0bbdccSNobuhiro Iwamatsu * Configuation settings for the Hitachi Solution Engine 7722 36c0bbdccSNobuhiro Iwamatsu * 46c0bbdccSNobuhiro Iwamatsu * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 56c0bbdccSNobuhiro Iwamatsu * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 76c0bbdccSNobuhiro Iwamatsu */ 86c0bbdccSNobuhiro Iwamatsu 96c0bbdccSNobuhiro Iwamatsu #ifndef __MS7722SE_H 106c0bbdccSNobuhiro Iwamatsu #define __MS7722SE_H 116c0bbdccSNobuhiro Iwamatsu 126c0bbdccSNobuhiro Iwamatsu #define CONFIG_CPU_SH7722 1 136c0bbdccSNobuhiro Iwamatsu #define CONFIG_MS7722SE 1 146c0bbdccSNobuhiro Iwamatsu 155783758fSNobuhiro Iwamatsu #define CONFIG_CMD_JFFS2 166c0bbdccSNobuhiro Iwamatsu #define CONFIG_CMD_SDRAM 176c0bbdccSNobuhiro Iwamatsu 186c0bbdccSNobuhiro Iwamatsu #define CONFIG_BAUDRATE 115200 196c0bbdccSNobuhiro Iwamatsu #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" 206c0bbdccSNobuhiro Iwamatsu 21*18a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 226c0bbdccSNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 236c0bbdccSNobuhiro Iwamatsu 246c0bbdccSNobuhiro Iwamatsu /* SMC9111 */ 257194ab80SBen Warren #define CONFIG_SMC91111 266c0bbdccSNobuhiro Iwamatsu #define CONFIG_SMC91111_BASE (0xB8000000) 276c0bbdccSNobuhiro Iwamatsu 286c0bbdccSNobuhiro Iwamatsu /* MEMORY */ 296c0bbdccSNobuhiro Iwamatsu #define MS7722SE_SDRAM_BASE (0x8C000000) 306c0bbdccSNobuhiro Iwamatsu #define MS7722SE_FLASH_BASE_1 (0xA0000000) 316c0bbdccSNobuhiro Iwamatsu #define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) 326c0bbdccSNobuhiro Iwamatsu 335c1877d6SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ 396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 406c0bbdccSNobuhiro Iwamatsu 416c0bbdccSNobuhiro Iwamatsu /* SCIF */ 426c58a030SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SCIF_CONSOLE 1 436c0bbdccSNobuhiro Iwamatsu #define CONFIG_CONS_SCIF0 1 446c0bbdccSNobuhiro Iwamatsu 456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE) 466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 476c0bbdccSNobuhiro Iwamatsu 486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_ALT_MEMTEST /* Enable alternate, more extensive, memory test */ 496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */ 506c0bbdccSNobuhiro Iwamatsu 516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */ 526c0bbdccSNobuhiro Iwamatsu 536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE) 546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */ 556c0bbdccSNobuhiro Iwamatsu 566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ 576c0bbdccSNobuhiro Iwamatsu 586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image 596c0bbdccSNobuhiro Iwamatsu in Flash (NOT run time address in SDRAM) ?!? */ 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */ 616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ 626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 636c0bbdccSNobuhiro Iwamatsu 646c0bbdccSNobuhiro Iwamatsu /* FLASH */ 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 6600b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_QUIET_TEST 686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 696c0bbdccSNobuhiro Iwamatsu 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ 716c0bbdccSNobuhiro Iwamatsu 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each 736c0bbdccSNobuhiro Iwamatsu Flash chip */ 746c0bbdccSNobuhiro Iwamatsu 756c0bbdccSNobuhiro Iwamatsu /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \ 786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \ 796c0bbdccSNobuhiro Iwamatsu } 806c0bbdccSNobuhiro Iwamatsu 816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */ 826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */ 836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */ 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */ 856c0bbdccSNobuhiro Iwamatsu 866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */ 876c0bbdccSNobuhiro Iwamatsu 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_DIRECT_FLASH_TFTP 896c0bbdccSNobuhiro Iwamatsu 905a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 916c0bbdccSNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 920e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE (8 * 1024) 930e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 960e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 986c0bbdccSNobuhiro Iwamatsu 996c0bbdccSNobuhiro Iwamatsu /* Board Clock */ 1006c0bbdccSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 33333333 101684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 102684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 103be45c632SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ 1046c0bbdccSNobuhiro Iwamatsu 1056c0bbdccSNobuhiro Iwamatsu #endif /* __MS7722SE_H */ 106