1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a4884831SStefan Roese /* 3a4884831SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 4a4884831SStefan Roese */ 5a4884831SStefan Roese 6a4884831SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 7a4884831SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 8a4884831SStefan Roese 9a4884831SStefan Roese /* 10a4884831SStefan Roese * High Level Configuration Options (easy to change) 11a4884831SStefan Roese */ 12a4884831SStefan Roese 132923c2d2SStefan Roese /* 142923c2d2SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 152923c2d2SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 162923c2d2SStefan Roese * U-Boot into it. 172923c2d2SStefan Roese */ 18a4884831SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 19a4884831SStefan Roese 20a4884831SStefan Roese /* 21a4884831SStefan Roese * Commands configuration 22a4884831SStefan Roese */ 23a4884831SStefan Roese 24a4884831SStefan Roese /* I2C */ 25a4884831SStefan Roese #define CONFIG_SYS_I2C 26a4884831SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 27dd82242bSPaul Kocialkowski #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 28a4884831SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 29a4884831SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 30a4884831SStefan Roese 31a4884831SStefan Roese /* SPI NOR flash default params, used by sf commands */ 32a4884831SStefan Roese 33a4884831SStefan Roese /* Environment in SPI NOR flash */ 34a4884831SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 35a4884831SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 36a4884831SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 37a4884831SStefan Roese 38a4884831SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 39a4884831SStefan Roese 40a4884831SStefan Roese /* 41a4884831SStefan Roese * mv-common.h should be defined after CMD configs since it used them 42a4884831SStefan Roese * to enable certain macros 43a4884831SStefan Roese */ 44a4884831SStefan Roese #include "mv-common.h" 45a4884831SStefan Roese 46e7778ec1SStefan Roese /* 47e7778ec1SStefan Roese * Memory layout while starting into the bin_hdr via the 48e7778ec1SStefan Roese * BootROM: 49e7778ec1SStefan Roese * 50e7778ec1SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 51e7778ec1SStefan Roese * 0x4000.4030 bin_hdr start address 52e7778ec1SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 53e7778ec1SStefan Roese * 0x4007.fffc BootROM stack top 54e7778ec1SStefan Roese * 55e7778ec1SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 56e7778ec1SStefan Roese * L2 cache thus cannot be used. 57e7778ec1SStefan Roese */ 58e7778ec1SStefan Roese 59e7778ec1SStefan Roese /* SPL */ 60e7778ec1SStefan Roese /* Defines for SPL */ 61e7778ec1SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 62e7778ec1SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 63e7778ec1SStefan Roese 64e7778ec1SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 65e7778ec1SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 66e7778ec1SStefan Roese 676451223aSStefan Roese #ifdef CONFIG_SPL_BUILD 686451223aSStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 696451223aSStefan Roese #endif 70e7778ec1SStefan Roese 71e7778ec1SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 72e7778ec1SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 73e7778ec1SStefan Roese 74e7778ec1SStefan Roese /* SPL related SPI defines */ 75e7778ec1SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 76e7778ec1SStefan Roese 77e7778ec1SStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 78e7778ec1SStefan Roese #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 79698ffab2SStefan Roese #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 80e7778ec1SStefan Roese 81a4884831SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 82