1*58c3e620SPriyanka Jain /* SPDX-License-Identifier: GPL-2.0+ */ 2*58c3e620SPriyanka Jain /* 3*58c3e620SPriyanka Jain * Copyright 2018 NXP 4*58c3e620SPriyanka Jain */ 5*58c3e620SPriyanka Jain 6*58c3e620SPriyanka Jain #ifndef __LX2_RDB_H 7*58c3e620SPriyanka Jain #define __LX2_RDB_H 8*58c3e620SPriyanka Jain 9*58c3e620SPriyanka Jain #include "lx2160a_common.h" 10*58c3e620SPriyanka Jain 11*58c3e620SPriyanka Jain /* Qixis */ 12*58c3e620SPriyanka Jain #define QIXIS_XMAP_MASK 0x07 13*58c3e620SPriyanka Jain #define QIXIS_XMAP_SHIFT 5 14*58c3e620SPriyanka Jain #define QIXIS_RST_CTL_RESET_EN 0x30 15*58c3e620SPriyanka Jain #define QIXIS_LBMAP_DFLTBANK 0x00 16*58c3e620SPriyanka Jain #define QIXIS_LBMAP_ALTBANK 0x20 17*58c3e620SPriyanka Jain #define QIXIS_LBMAP_QSPI 0x00 18*58c3e620SPriyanka Jain #define QIXIS_RCW_SRC_QSPI 0xff 19*58c3e620SPriyanka Jain #define QIXIS_RST_CTL_RESET 0x31 20*58c3e620SPriyanka Jain #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 21*58c3e620SPriyanka Jain #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 22*58c3e620SPriyanka Jain #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 23*58c3e620SPriyanka Jain #define QIXIS_LBMAP_MASK 0x0f 24*58c3e620SPriyanka Jain #define QIXIS_LBMAP_SD 25*58c3e620SPriyanka Jain #define QIXIS_RCW_SRC_SD 0x08 26*58c3e620SPriyanka Jain #define NON_EXTENDED_DUTCFG 27*58c3e620SPriyanka Jain 28*58c3e620SPriyanka Jain /* VID */ 29*58c3e620SPriyanka Jain 30*58c3e620SPriyanka Jain #define I2C_MUX_CH_VOL_MONITOR 0xA 31*58c3e620SPriyanka Jain /* Voltage monitor on channel 2*/ 32*58c3e620SPriyanka Jain #define I2C_VOL_MONITOR_ADDR 0x63 33*58c3e620SPriyanka Jain #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 34*58c3e620SPriyanka Jain #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 35*58c3e620SPriyanka Jain #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 36*58c3e620SPriyanka Jain #define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" 37*58c3e620SPriyanka Jain #define CONFIG_VID 38*58c3e620SPriyanka Jain 39*58c3e620SPriyanka Jain /* The lowest and highest voltage allowed*/ 40*58c3e620SPriyanka Jain #define VDD_MV_MIN 775 41*58c3e620SPriyanka Jain #define VDD_MV_MAX 855 42*58c3e620SPriyanka Jain 43*58c3e620SPriyanka Jain /* PM Bus commands code for LTC3882*/ 44*58c3e620SPriyanka Jain #define PMBUS_CMD_PAGE 0x0 45*58c3e620SPriyanka Jain #define PMBUS_CMD_READ_VOUT 0x8B 46*58c3e620SPriyanka Jain #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 47*58c3e620SPriyanka Jain #define PMBUS_CMD_VOUT_COMMAND 0x21 48*58c3e620SPriyanka Jain #define PWM_CHANNEL0 0x0 49*58c3e620SPriyanka Jain 50*58c3e620SPriyanka Jain #define CONFIG_VOL_MONITOR_LTC3882_SET 51*58c3e620SPriyanka Jain #define CONFIG_VOL_MONITOR_LTC3882_READ 52*58c3e620SPriyanka Jain 53*58c3e620SPriyanka Jain /* RTC */ 54*58c3e620SPriyanka Jain #define CONFIG_SYS_RTC_BUS_NUM 4 55*58c3e620SPriyanka Jain 56*58c3e620SPriyanka Jain /* MAC/PHY configuration */ 57*58c3e620SPriyanka Jain #if defined(CONFIG_FSL_MC_ENET) 58*58c3e620SPriyanka Jain #define CONFIG_MII 59*58c3e620SPriyanka Jain #define CONFIG_ETHPRIME "DPMAC1@xgmii" 60*58c3e620SPriyanka Jain 61*58c3e620SPriyanka Jain #define AQR107_PHY_ADDR1 0x04 62*58c3e620SPriyanka Jain #define AQR107_PHY_ADDR2 0x05 63*58c3e620SPriyanka Jain 64*58c3e620SPriyanka Jain #define CORTINA_NO_FW_UPLOAD 65*58c3e620SPriyanka Jain #define CORTINA_PHY_ADDR1 0x0 66*58c3e620SPriyanka Jain #define INPHI_PHY_ADDR1 0x0 67*58c3e620SPriyanka Jain 68*58c3e620SPriyanka Jain #define RGMII_PHY_ADDR1 0x01 69*58c3e620SPriyanka Jain #define RGMII_PHY_ADDR2 0x02 70*58c3e620SPriyanka Jain 71*58c3e620SPriyanka Jain #endif 72*58c3e620SPriyanka Jain 73*58c3e620SPriyanka Jain /* EEPROM */ 74*58c3e620SPriyanka Jain #define CONFIG_ID_EEPROM 75*58c3e620SPriyanka Jain #define CONFIG_SYS_I2C_EEPROM_NXID 76*58c3e620SPriyanka Jain #define CONFIG_SYS_EEPROM_BUS_NUM 0 77*58c3e620SPriyanka Jain #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 78*58c3e620SPriyanka Jain #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 79*58c3e620SPriyanka Jain #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 80*58c3e620SPriyanka Jain #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 81*58c3e620SPriyanka Jain 82*58c3e620SPriyanka Jain /* Initial environment variables */ 83*58c3e620SPriyanka Jain #define CONFIG_EXTRA_ENV_SETTINGS \ 84*58c3e620SPriyanka Jain "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 85*58c3e620SPriyanka Jain "scriptaddr=0x80800000\0" \ 86*58c3e620SPriyanka Jain "kernel_addr_r=0x81000000\0" \ 87*58c3e620SPriyanka Jain "pxefile_addr_r=0x81000000\0" \ 88*58c3e620SPriyanka Jain "fdt_addr_r=0x88000000\0" \ 89*58c3e620SPriyanka Jain "ramdisk_addr_r=0x89000000\0" \ 90*58c3e620SPriyanka Jain "loadaddr=0x80100000\0" \ 91*58c3e620SPriyanka Jain "kernel_addr=0x100000\0" \ 92*58c3e620SPriyanka Jain "ramdisk_addr=0x800000\0" \ 93*58c3e620SPriyanka Jain "ramdisk_size=0x2000000\0" \ 94*58c3e620SPriyanka Jain "fdt_high=0xa0000000\0" \ 95*58c3e620SPriyanka Jain "initrd_high=0xffffffffffffffff\0" \ 96*58c3e620SPriyanka Jain "kernel_start=0x21000000\0" \ 97*58c3e620SPriyanka Jain "lx2160ardb_vdd_mv=800\0" \ 98*58c3e620SPriyanka Jain "mcmemsize=0x40000000\0" 99*58c3e620SPriyanka Jain 100*58c3e620SPriyanka Jain #include <asm/fsl_secure_boot.h> 101*58c3e620SPriyanka Jain 102*58c3e620SPriyanka Jain #endif /* __LX2_RDB_H */ 103