158c3e620SPriyanka Jain /* SPDX-License-Identifier: GPL-2.0+ */ 258c3e620SPriyanka Jain /* 358c3e620SPriyanka Jain * Copyright 2018 NXP 458c3e620SPriyanka Jain */ 558c3e620SPriyanka Jain 658c3e620SPriyanka Jain #ifndef __LX2_RDB_H 758c3e620SPriyanka Jain #define __LX2_RDB_H 858c3e620SPriyanka Jain 958c3e620SPriyanka Jain #include "lx2160a_common.h" 1058c3e620SPriyanka Jain 1158c3e620SPriyanka Jain /* Qixis */ 1258c3e620SPriyanka Jain #define QIXIS_XMAP_MASK 0x07 1358c3e620SPriyanka Jain #define QIXIS_XMAP_SHIFT 5 1458c3e620SPriyanka Jain #define QIXIS_RST_CTL_RESET_EN 0x30 1558c3e620SPriyanka Jain #define QIXIS_LBMAP_DFLTBANK 0x00 1658c3e620SPriyanka Jain #define QIXIS_LBMAP_ALTBANK 0x20 1758c3e620SPriyanka Jain #define QIXIS_LBMAP_QSPI 0x00 1858c3e620SPriyanka Jain #define QIXIS_RCW_SRC_QSPI 0xff 1958c3e620SPriyanka Jain #define QIXIS_RST_CTL_RESET 0x31 2058c3e620SPriyanka Jain #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 2158c3e620SPriyanka Jain #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 2258c3e620SPriyanka Jain #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 2358c3e620SPriyanka Jain #define QIXIS_LBMAP_MASK 0x0f 2458c3e620SPriyanka Jain #define QIXIS_LBMAP_SD 2558c3e620SPriyanka Jain #define QIXIS_RCW_SRC_SD 0x08 2658c3e620SPriyanka Jain #define NON_EXTENDED_DUTCFG 2758c3e620SPriyanka Jain 2858c3e620SPriyanka Jain /* VID */ 2958c3e620SPriyanka Jain 3058c3e620SPriyanka Jain #define I2C_MUX_CH_VOL_MONITOR 0xA 3158c3e620SPriyanka Jain /* Voltage monitor on channel 2*/ 3258c3e620SPriyanka Jain #define I2C_VOL_MONITOR_ADDR 0x63 3358c3e620SPriyanka Jain #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 3458c3e620SPriyanka Jain #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 3558c3e620SPriyanka Jain #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 3658c3e620SPriyanka Jain #define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" 3758c3e620SPriyanka Jain #define CONFIG_VID 3858c3e620SPriyanka Jain 3958c3e620SPriyanka Jain /* The lowest and highest voltage allowed*/ 4058c3e620SPriyanka Jain #define VDD_MV_MIN 775 4158c3e620SPriyanka Jain #define VDD_MV_MAX 855 4258c3e620SPriyanka Jain 4358c3e620SPriyanka Jain /* PM Bus commands code for LTC3882*/ 4458c3e620SPriyanka Jain #define PMBUS_CMD_PAGE 0x0 4558c3e620SPriyanka Jain #define PMBUS_CMD_READ_VOUT 0x8B 4658c3e620SPriyanka Jain #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 4758c3e620SPriyanka Jain #define PMBUS_CMD_VOUT_COMMAND 0x21 4858c3e620SPriyanka Jain #define PWM_CHANNEL0 0x0 4958c3e620SPriyanka Jain 5058c3e620SPriyanka Jain #define CONFIG_VOL_MONITOR_LTC3882_SET 5158c3e620SPriyanka Jain #define CONFIG_VOL_MONITOR_LTC3882_READ 5258c3e620SPriyanka Jain 5358c3e620SPriyanka Jain /* RTC */ 5458c3e620SPriyanka Jain #define CONFIG_SYS_RTC_BUS_NUM 4 5558c3e620SPriyanka Jain 5658c3e620SPriyanka Jain /* MAC/PHY configuration */ 5758c3e620SPriyanka Jain #if defined(CONFIG_FSL_MC_ENET) 5858c3e620SPriyanka Jain #define CONFIG_MII 5958c3e620SPriyanka Jain #define CONFIG_ETHPRIME "DPMAC1@xgmii" 6058c3e620SPriyanka Jain 6158c3e620SPriyanka Jain #define AQR107_PHY_ADDR1 0x04 6258c3e620SPriyanka Jain #define AQR107_PHY_ADDR2 0x05 6358c3e620SPriyanka Jain 6458c3e620SPriyanka Jain #define CORTINA_NO_FW_UPLOAD 6558c3e620SPriyanka Jain #define CORTINA_PHY_ADDR1 0x0 6658c3e620SPriyanka Jain #define INPHI_PHY_ADDR1 0x0 6758c3e620SPriyanka Jain 6858c3e620SPriyanka Jain #define RGMII_PHY_ADDR1 0x01 6958c3e620SPriyanka Jain #define RGMII_PHY_ADDR2 0x02 7058c3e620SPriyanka Jain 7158c3e620SPriyanka Jain #endif 7258c3e620SPriyanka Jain 73938e35e5SMeenakshi Aggarwal /* EMC2305 */ 74938e35e5SMeenakshi Aggarwal #define I2C_MUX_CH_EMC2305 0x09 75938e35e5SMeenakshi Aggarwal #define I2C_EMC2305_ADDR 0x4D 76938e35e5SMeenakshi Aggarwal #define I2C_EMC2305_CMD 0x40 77938e35e5SMeenakshi Aggarwal #define I2C_EMC2305_PWM 0x80 78938e35e5SMeenakshi Aggarwal 7958c3e620SPriyanka Jain /* EEPROM */ 8058c3e620SPriyanka Jain #define CONFIG_ID_EEPROM 8158c3e620SPriyanka Jain #define CONFIG_SYS_I2C_EEPROM_NXID 8258c3e620SPriyanka Jain #define CONFIG_SYS_EEPROM_BUS_NUM 0 8358c3e620SPriyanka Jain #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 8458c3e620SPriyanka Jain #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 8558c3e620SPriyanka Jain #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 8658c3e620SPriyanka Jain #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 8758c3e620SPriyanka Jain 8858c3e620SPriyanka Jain /* Initial environment variables */ 8958c3e620SPriyanka Jain #define CONFIG_EXTRA_ENV_SETTINGS \ 90*3e1a9b5cSPriyanka Jain EXTRA_ENV_SETTINGS \ 9158c3e620SPriyanka Jain "lx2160ardb_vdd_mv=800\0" \ 92*3e1a9b5cSPriyanka Jain "BOARD=lx2160ardb\0" \ 93*3e1a9b5cSPriyanka Jain "xspi_bootcmd=echo Trying load from flexspi..;" \ 94*3e1a9b5cSPriyanka Jain "sf probe 0:0 && sf read $load_addr " \ 95*3e1a9b5cSPriyanka Jain "$kernel_start $kernel_size ; env exists secureboot &&" \ 96*3e1a9b5cSPriyanka Jain "sf read $kernelheader_addr_r $kernelheader_start " \ 97*3e1a9b5cSPriyanka Jain "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ 98*3e1a9b5cSPriyanka Jain " bootm $load_addr#$BOARD\0" \ 99*3e1a9b5cSPriyanka Jain "sd_bootcmd=echo Trying load from sd card..;" \ 100*3e1a9b5cSPriyanka Jain "mmcinfo; mmc read $load_addr " \ 101*3e1a9b5cSPriyanka Jain "$kernel_addr_sd $kernel_size_sd ;" \ 102*3e1a9b5cSPriyanka Jain "env exists secureboot && mmc read $kernelheader_addr_r "\ 103*3e1a9b5cSPriyanka Jain "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 104*3e1a9b5cSPriyanka Jain " && esbc_validate ${kernelheader_addr_r};" \ 105*3e1a9b5cSPriyanka Jain "bootm $load_addr#$BOARD\0" 10658c3e620SPriyanka Jain 10758c3e620SPriyanka Jain #include <asm/fsl_secure_boot.h> 10858c3e620SPriyanka Jain 10958c3e620SPriyanka Jain #endif /* __LX2_RDB_H */ 110