1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 244937214SPrabhakar Kushwaha /* 344937214SPrabhakar Kushwaha * Copyright 2014 Freescale Semiconductor 444937214SPrabhakar Kushwaha */ 544937214SPrabhakar Kushwaha 644937214SPrabhakar Kushwaha #ifndef __LS2_EMU_H 744937214SPrabhakar Kushwaha #define __LS2_EMU_H 844937214SPrabhakar Kushwaha 944937214SPrabhakar Kushwaha #include "ls2080a_common.h" 1044937214SPrabhakar Kushwaha 1144937214SPrabhakar Kushwaha #define CONFIG_SYS_CLK_FREQ 100000000 1244937214SPrabhakar Kushwaha #define CONFIG_DDR_CLK_FREQ 133333333 1344937214SPrabhakar Kushwaha 1444937214SPrabhakar Kushwaha #define CONFIG_DDR_SPD 1544937214SPrabhakar Kushwaha #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ 1644937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS1 0x51 1744937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS2 0x52 1844937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS3 0x53 1944937214SPrabhakar Kushwaha #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 2044937214SPrabhakar Kushwaha #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ 2144937214SPrabhakar Kushwaha #define CONFIG_DIMM_SLOTS_PER_CTLR 1 2244937214SPrabhakar Kushwaha #define CONFIG_CHIP_SELECTS_PER_CTRL 4 2344937214SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 2444937214SPrabhakar Kushwaha #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 2544937214SPrabhakar Kushwaha #endif 2644937214SPrabhakar Kushwaha 2744937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 2844937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 2944937214SPrabhakar Kushwaha /* 3044937214SPrabhakar Kushwaha * NOR Flash Timing Params 3144937214SPrabhakar Kushwaha */ 3244937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR \ 3344937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 3444937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 3544937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 3644937214SPrabhakar Kushwaha CSPR_V) 3744937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR0_CSPR_EARLY \ 3844937214SPrabhakar Kushwaha (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 3944937214SPrabhakar Kushwaha CSPR_PORT_SIZE_16 | \ 4044937214SPrabhakar Kushwaha CSPR_MSEL_NOR | \ 4144937214SPrabhakar Kushwaha CSPR_V) 4244937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 4344937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 4444937214SPrabhakar Kushwaha FTIM0_NOR_TEADC(0x1) | \ 4544937214SPrabhakar Kushwaha FTIM0_NOR_TEAHC(0x1)) 4644937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 4744937214SPrabhakar Kushwaha FTIM1_NOR_TRAD_NOR(0x1)) 4844937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 4944937214SPrabhakar Kushwaha FTIM2_NOR_TCH(0x0) | \ 5044937214SPrabhakar Kushwaha FTIM2_NOR_TWP(0x1)) 5144937214SPrabhakar Kushwaha #define CONFIG_SYS_NOR_FTIM3 0x04000000 5244937214SPrabhakar Kushwaha #define CONFIG_SYS_IFC_CCR 0x01000000 5344937214SPrabhakar Kushwaha 5444937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 5544937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 5644937214SPrabhakar Kushwaha #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 5744937214SPrabhakar Kushwaha #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 5844937214SPrabhakar Kushwaha #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 5944937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 6044937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 6144937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 6244937214SPrabhakar Kushwaha #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 6344937214SPrabhakar Kushwaha 6444937214SPrabhakar Kushwaha /* Debug Server firmware */ 6544937214SPrabhakar Kushwaha #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 6644937214SPrabhakar Kushwaha #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL 6744937214SPrabhakar Kushwaha 6844937214SPrabhakar Kushwaha /* 6944937214SPrabhakar Kushwaha * This trick allows users to load MC images into DDR directly without 7044937214SPrabhakar Kushwaha * copying from NOR flash. It dramatically improves speed. 7144937214SPrabhakar Kushwaha */ 7244937214SPrabhakar Kushwaha #define CONFIG_SYS_LS_MC_FW_IN_DDR 7344937214SPrabhakar Kushwaha #define CONFIG_SYS_LS_MC_DPL_IN_DDR 7444937214SPrabhakar Kushwaha #define CONFIG_SYS_LS_MC_DPC_IN_DDR 7544937214SPrabhakar Kushwaha 7644937214SPrabhakar Kushwaha #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 7744937214SPrabhakar Kushwaha 7844937214SPrabhakar Kushwaha /* Store environment at top of flash */ 7944937214SPrabhakar Kushwaha #define CONFIG_ENV_SIZE 0x1000 8044937214SPrabhakar Kushwaha 8144937214SPrabhakar Kushwaha #endif /* __LS2_EMU_H */ 82