1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_FSL_LSCH3 13 #define CONFIG_MP 14 #define CONFIG_GICV3 15 #define CONFIG_FSL_TZPC_BP147 16 17 #include <asm/arch/ls2080a_stream_id.h> 18 #include <asm/arch/config.h> 19 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) 20 #define CONFIG_SYS_HAS_SERDES 21 #endif 22 23 /* Link Definitions */ 24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 25 26 /* We need architecture specific misc initializations */ 27 #define CONFIG_ARCH_MISC_INIT 28 29 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 30 31 /* Link Definitions */ 32 #ifndef CONFIG_QSPI_BOOT 33 #ifdef CONFIG_SPL 34 #define CONFIG_SYS_TEXT_BASE 0x80400000 35 #else 36 #define CONFIG_SYS_TEXT_BASE 0x30100000 37 #endif 38 #endif 39 40 #ifdef CONFIG_EMU 41 #define CONFIG_SYS_NO_FLASH 42 #endif 43 44 #define CONFIG_SUPPORT_RAW_INITRD 45 46 #define CONFIG_SKIP_LOWLEVEL_INIT 47 #define CONFIG_BOARD_EARLY_INIT_F 1 48 49 #ifndef CONFIG_SPL 50 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 51 #endif 52 #ifndef CONFIG_SYS_FSL_DDR4 53 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 54 #define CONFIG_SYS_DDR_RAW_TIMING 55 #endif 56 57 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 58 59 #define CONFIG_VERY_BIG_RAM 60 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 61 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 64 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 65 66 /* 67 * SMP Definitinos 68 */ 69 #define CPU_RELEASE_ADDR secondary_boot_func 70 71 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 72 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 73 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 74 /* 75 * DDR controller use 0 as the base address for binding. 76 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 77 */ 78 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 79 #define CONFIG_DP_DDR_CTRL 2 80 #define CONFIG_DP_DDR_NUM_CTRLS 1 81 #endif 82 83 /* Generic Timer Definitions */ 84 /* 85 * This is not an accurate number. It is used in start.S. The frequency 86 * will be udpated later when get_bus_freq(0) is available. 87 */ 88 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 89 90 /* Size of malloc() pool */ 91 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 92 93 /* I2C */ 94 #define CONFIG_SYS_I2C 95 #define CONFIG_SYS_I2C_MXC 96 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 97 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 98 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 99 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 100 101 /* Serial Port */ 102 #define CONFIG_CONS_INDEX 1 103 #define CONFIG_SYS_NS16550_SERIAL 104 #define CONFIG_SYS_NS16550_REG_SIZE 1 105 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 106 107 #define CONFIG_BAUDRATE 115200 108 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 109 110 /* IFC */ 111 #define CONFIG_FSL_IFC 112 113 /* 114 * During booting, IFC is mapped at the region of 0x30000000. 115 * But this region is limited to 256MB. To accommodate NOR, promjet 116 * and FPGA. This region is divided as below: 117 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 118 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 119 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 120 * 121 * To accommodate bigger NOR flash and other devices, we will map IFC 122 * chip selects to as below: 123 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 124 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 125 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 126 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 127 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 128 * 129 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 130 * CONFIG_SYS_FLASH_BASE has the final address (core view) 131 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 132 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 133 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 134 */ 135 136 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 137 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 138 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 139 140 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 141 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 142 143 #ifndef __ASSEMBLY__ 144 unsigned long long get_qixis_addr(void); 145 #endif 146 #define QIXIS_BASE get_qixis_addr() 147 #define QIXIS_BASE_PHYS 0x20000000 148 #define QIXIS_BASE_PHYS_EARLY 0xC000000 149 #define QIXIS_STAT_PRES1 0xb 150 #define QIXIS_SDID_MASK 0x07 151 #define QIXIS_ESDHC_NO_ADAPTER 0x7 152 153 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 154 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 155 156 /* MC firmware */ 157 #define CONFIG_FSL_MC_ENET 158 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 159 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 160 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 161 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 162 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 163 /* For LS2085A */ 164 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 165 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 166 167 /* 168 * Carve out a DDR region which will not be used by u-boot/Linux 169 * 170 * It will be used by MC and Debug Server. The MC region must be 171 * 512MB aligned, so the min size to hide is 512MB. 172 */ 173 #ifdef CONFIG_FSL_MC_ENET 174 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 175 #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) 176 #endif 177 178 /* PCIe */ 179 #define CONFIG_PCIE1 /* PCIE controller 1 */ 180 #define CONFIG_PCIE2 /* PCIE controller 2 */ 181 #define CONFIG_PCIE3 /* PCIE controller 3 */ 182 #define CONFIG_PCIE4 /* PCIE controller 4 */ 183 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 184 #ifdef CONFIG_LS2080A 185 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" 186 #endif 187 188 #define CONFIG_SYS_PCI_64BIT 189 190 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 191 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 192 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 193 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 194 195 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 196 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 197 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 198 199 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 200 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 201 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 202 203 /* Command line configuration */ 204 #define CONFIG_CMD_ENV 205 206 /* Miscellaneous configurable options */ 207 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 208 #define CONFIG_ARCH_EARLY_INIT_R 209 210 /* Physical Memory Map */ 211 /* fixme: these need to be checked against the board */ 212 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 213 214 #define CONFIG_NR_DRAM_BANKS 3 215 216 #define CONFIG_HWCONFIG 217 #define HWCONFIG_BUFFER_SIZE 128 218 219 #define CONFIG_DISPLAY_CPUINFO 220 221 /* Allow to overwrite serial and ethaddr */ 222 #define CONFIG_ENV_OVERWRITE 223 224 /* Initial environment variables */ 225 #define CONFIG_EXTRA_ENV_SETTINGS \ 226 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 227 "loadaddr=0x80100000\0" \ 228 "kernel_addr=0x100000\0" \ 229 "ramdisk_addr=0x800000\0" \ 230 "ramdisk_size=0x2000000\0" \ 231 "fdt_high=0xa0000000\0" \ 232 "initrd_high=0xffffffffffffffff\0" \ 233 "kernel_start=0x581200000\0" \ 234 "kernel_load=0xa0000000\0" \ 235 "kernel_size=0x2800000\0" \ 236 "console=ttyAMA0,38400n8\0" \ 237 "mcinitcmd=fsl_mc start mc 0x580300000" \ 238 " 0x580800000 \0" 239 240 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 241 "earlycon=uart8250,mmio,0x21c0500 " \ 242 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 243 " hugepagesz=2m hugepages=256" 244 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ 245 " cp.b $kernel_start $kernel_load" \ 246 " $kernel_size && bootm $kernel_load" 247 248 /* Monitor Command Prompt */ 249 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 250 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 251 sizeof(CONFIG_SYS_PROMPT) + 16) 252 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 253 #define CONFIG_SYS_LONGHELP 254 #define CONFIG_CMDLINE_EDITING 1 255 #define CONFIG_AUTO_COMPLETE 256 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 257 258 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 259 260 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 261 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 262 #define CONFIG_SPL_FRAMEWORK 263 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 264 #define CONFIG_SPL_MAX_SIZE 0x16000 265 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 266 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 267 #define CONFIG_SPL_TEXT_BASE 0x1800a000 268 269 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 270 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 271 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 272 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 273 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) 274 275 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 276 277 /* Hash command with SHA acceleration supported in hardware */ 278 #ifdef CONFIG_FSL_CAAM 279 #define CONFIG_CMD_HASH 280 #define CONFIG_SHA_HW_ACCEL 281 #endif 282 283 #endif /* __LS2_COMMON_H */ 284