1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12 #define CONFIG_SYS_FSL_CLK 13 14 /* 15 * Size of malloc() pool 16 */ 17 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 18 19 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 20 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 21 22 #define CONFIG_SYS_CLK_FREQ 100000000 23 #define CONFIG_DDR_CLK_FREQ 100000000 24 25 /* 26 * DDR: 800 MHz ( 1600 MT/s data rate ) 27 */ 28 29 #define DDR_SDRAM_CFG 0x470c0008 30 #define DDR_CS0_BNDS 0x008000bf 31 #define DDR_CS0_CONFIG 0x80014302 32 #define DDR_TIMING_CFG_0 0x50550004 33 #define DDR_TIMING_CFG_1 0xbcb38c56 34 #define DDR_TIMING_CFG_2 0x0040d120 35 #define DDR_TIMING_CFG_3 0x010e1000 36 #define DDR_TIMING_CFG_4 0x00000001 37 #define DDR_TIMING_CFG_5 0x03401400 38 #define DDR_SDRAM_CFG_2 0x00401010 39 #define DDR_SDRAM_MODE 0x00061c60 40 #define DDR_SDRAM_MODE_2 0x00180000 41 #define DDR_SDRAM_INTERVAL 0x18600618 42 #define DDR_DDR_WRLVL_CNTL 0x8655f605 43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 45 #define DDR_DDR_CDR1 0x80040000 46 #define DDR_DDR_CDR2 0x00000001 47 #define DDR_SDRAM_CLK_CNTL 0x02000000 48 #define DDR_DDR_ZQ_CNTL 0x89080600 49 #define DDR_CS0_CONFIG_2 0 50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 51 #define SDRAM_CFG2_D_INIT 0x00000010 52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 53 #define SDRAM_CFG2_FRC_SR 0x80000000 54 #define SDRAM_CFG_BI 0x00000001 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI \ 58 board/freescale/ls1021aiot/ls102xa_pbi.cfg 59 #endif 60 61 #ifdef CONFIG_SD_BOOT 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 64 #define CONFIG_SPL_LIBCOMMON_SUPPORT 65 #define CONFIG_SPL_LIBGENERIC_SUPPORT 66 #define CONFIG_SPL_ENV_SUPPORT 67 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 68 #define CONFIG_SPL_I2C_SUPPORT 69 #define CONFIG_SPL_WATCHDOG_SUPPORT 70 #define CONFIG_SPL_MMC_SUPPORT 71 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 72 73 #define CONFIG_SPL_TEXT_BASE 0x10000000 74 #define CONFIG_SPL_MAX_SIZE 0x1a000 75 #define CONFIG_SPL_STACK 0x1001d000 76 #define CONFIG_SPL_PAD_TO 0x1c000 77 78 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 79 CONFIG_SYS_MONITOR_LEN) 80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 83 #define CONFIG_SYS_MONITOR_LEN 0x80000 84 #endif 85 86 #define CONFIG_NR_DRAM_BANKS 1 87 88 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 90 91 /* 92 * Serial Port 93 */ 94 #define CONFIG_SYS_NS16550_SERIAL 95 #define CONFIG_SYS_NS16550_REG_SIZE 1 96 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 97 98 /* 99 * I2C 100 */ 101 #define CONFIG_CMD_I2C 102 #define CONFIG_SYS_I2C 103 #define CONFIG_SYS_I2C_MXC 104 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 105 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 106 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 107 108 /* EEPROM */ 109 #define CONFIG_ID_EEPROM 110 #define CONFIG_SYS_I2C_EEPROM_NXID 111 #define CONFIG_SYS_EEPROM_BUS_NUM 0 112 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 113 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 114 115 /* 116 * MMC 117 */ 118 #define CONFIG_CMD_MMC 119 120 /* SATA */ 121 #define CONFIG_SCSI_AHCI_PLAT 122 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI 123 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 124 #endif 125 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 126 PCI_DEVICE_ID_FREESCALE_AHCI} 127 128 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 129 #define CONFIG_SYS_SCSI_MAX_LUN 1 130 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 131 CONFIG_SYS_SCSI_MAX_LUN) 132 133 /* SPI */ 134 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 135 #define CONFIG_SPI_FLASH_SPANSION 136 137 /* QSPI */ 138 #define QSPI0_AMBA_BASE 0x40000000 139 #define FSL_QSPI_FLASH_SIZE (1 << 24) 140 #define FSL_QSPI_FLASH_NUM 2 141 #define CONFIG_SPI_FLASH_BAR 142 #define CONFIG_SPI_FLASH_SPANSION 143 #endif 144 145 /* DM SPI */ 146 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 147 #define CONFIG_CMD_SF 148 #define CONFIG_DM_SPI_FLASH 149 #endif 150 151 /* 152 * eTSEC 153 */ 154 155 #ifdef CONFIG_TSEC_ENET 156 #define CONFIG_MII 157 #define CONFIG_MII_DEFAULT_TSEC 1 158 #define CONFIG_TSEC1 1 159 #define CONFIG_TSEC1_NAME "eTSEC1" 160 #define CONFIG_TSEC2 1 161 #define CONFIG_TSEC2_NAME "eTSEC2" 162 163 #define TSEC1_PHY_ADDR 1 164 #define TSEC2_PHY_ADDR 3 165 166 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 167 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 168 169 #define TSEC1_PHYIDX 0 170 #define TSEC2_PHYIDX 0 171 172 #define CONFIG_ETHPRIME "eTSEC2" 173 174 #define CONFIG_PHY_ATHEROS 175 176 #define CONFIG_HAS_ETH0 177 #define CONFIG_HAS_ETH1 178 #define CONFIG_HAS_ETH2 179 #endif 180 181 /* PCIe */ 182 #define CONFIG_PCIE1 /* PCIE controler 1 */ 183 #define CONFIG_PCIE2 /* PCIE controler 2 */ 184 185 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 186 187 #ifdef CONFIG_PCI 188 #define CONFIG_PCI_SCAN_SHOW 189 #endif 190 191 #define CONFIG_CMD_MII 192 193 #define CONFIG_CMDLINE_TAG 194 195 #define CONFIG_PEN_ADDR_BIG_ENDIAN 196 #define CONFIG_LAYERSCAPE_NS_ACCESS 197 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 198 #define COUNTER_FREQUENCY 12500000 199 200 #define CONFIG_HWCONFIG 201 #define HWCONFIG_BUFFER_SIZE 256 202 203 #define CONFIG_FSL_DEVICE_DISABLE 204 205 #define CONFIG_EXTRA_ENV_SETTINGS \ 206 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 207 "initrd_high=0xffffffff\0" \ 208 "fdt_high=0xffffffff\0" 209 210 /* 211 * Miscellaneous configurable options 212 */ 213 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 214 215 #define CONFIG_CMD_GREPENV 216 #define CONFIG_CMD_MEMINFO 217 218 #define CONFIG_SYS_LOAD_ADDR 0x82000000 219 220 #define CONFIG_LS102XA_STREAM_ID 221 222 #define CONFIG_SYS_INIT_SP_OFFSET \ 223 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 224 #define CONFIG_SYS_INIT_SP_ADDR \ 225 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 226 227 #ifdef CONFIG_SPL_BUILD 228 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 229 #else 230 /* start of monitor */ 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 232 #endif 233 234 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 235 236 /* 237 * Environment 238 */ 239 240 #define CONFIG_ENV_OVERWRITE 241 242 #if defined(CONFIG_SD_BOOT) 243 #define CONFIG_ENV_OFFSET 0x100000 244 #define CONFIG_SYS_MMC_ENV_DEV 0 245 #define CONFIG_ENV_SIZE 0x2000 246 #elif defined(CONFIG_QSPI_BOOT) 247 #define CONFIG_ENV_SIZE 0x2000 248 #define CONFIG_ENV_OFFSET 0x100000 249 #define CONFIG_ENV_SECT_SIZE 0x10000 250 #endif 251 252 #define CONFIG_OF_BOARD_SETUP 253 #define CONFIG_OF_STDOUT_VIA_ALIAS 254 255 #define CONFIG_MISC_INIT_R 256 257 #include <asm/fsl_secure_boot.h> 258 259 #endif 260