xref: /openbmc/u-boot/include/configs/km/km_arm.h (revision 0e62d5b2abb69ddc9e58215e2d8dfa5d33996b8a)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2264eaa0eSValentin Longchamp /*
3264eaa0eSValentin Longchamp  * (C) Copyright 2009
4264eaa0eSValentin Longchamp  * Marvell Semiconductor <www.marvell.com>
5264eaa0eSValentin Longchamp  * Prafulla Wadaskar <prafulla@marvell.com>
6264eaa0eSValentin Longchamp  *
7264eaa0eSValentin Longchamp  * (C) Copyright 2009
8264eaa0eSValentin Longchamp  * Stefan Roese, DENX Software Engineering, sr@denx.de.
9264eaa0eSValentin Longchamp  *
10264eaa0eSValentin Longchamp  * (C) Copyright 2010-2011
11264eaa0eSValentin Longchamp  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12264eaa0eSValentin Longchamp  */
13264eaa0eSValentin Longchamp 
14264eaa0eSValentin Longchamp /*
15264eaa0eSValentin Longchamp  * for linking errors see
16264eaa0eSValentin Longchamp  * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
17264eaa0eSValentin Longchamp  */
18264eaa0eSValentin Longchamp 
19264eaa0eSValentin Longchamp #ifndef _CONFIG_KM_ARM_H
20264eaa0eSValentin Longchamp #define _CONFIG_KM_ARM_H
21264eaa0eSValentin Longchamp 
22264eaa0eSValentin Longchamp /*
23264eaa0eSValentin Longchamp  * High Level Configuration Options (easy to change)
24264eaa0eSValentin Longchamp  */
25264eaa0eSValentin Longchamp #define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
26264eaa0eSValentin Longchamp #define CONFIG_KW88F6281		/* SOC Name */
27264eaa0eSValentin Longchamp 
288620ca2aSValentin Longchamp #define CONFIG_MACH_TYPE	MACH_TYPE_KM_KIRKWOOD
298620ca2aSValentin Longchamp 
30dfeafde4SHolger Brunck #define CONFIG_NAND_ECC_BCH
31dfeafde4SHolger Brunck 
32264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */
33264eaa0eSValentin Longchamp #include "keymile-common.h"
34264eaa0eSValentin Longchamp 
35f46b4a1aSValentin Longchamp /* SPI NOR Flash default params, used by sf commands */
36f46b4a1aSValentin Longchamp 
37ac5b00e0SValentin Longchamp /* Reserve 4 MB for malloc */
38ac5b00e0SValentin Longchamp #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
39ac5b00e0SValentin Longchamp 
40b5befd82SHolger Brunck #include "asm/arch/config.h"
41b5befd82SHolger Brunck 
42264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
43264eaa0eSValentin Longchamp #define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
44264eaa0eSValentin Longchamp #define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
45264eaa0eSValentin Longchamp 
46264eaa0eSValentin Longchamp /* pseudo-non volatile RAM [hex] */
47264eaa0eSValentin Longchamp #define CONFIG_KM_PNVRAM	0x80000
48264eaa0eSValentin Longchamp /* physical RAM MTD size [hex] */
49264eaa0eSValentin Longchamp #define CONFIG_KM_PHRAM		0x17F000
50264eaa0eSValentin Longchamp 
51264eaa0eSValentin Longchamp #define CONFIG_KM_CRAMFS_ADDR	0x2400000
527b2268b8SGerlando Falauto #define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 3098KBytes */
537b2268b8SGerlando Falauto #define CONFIG_KM_FDT_ADDR	0x23E0000	/*  128KBytes */
54264eaa0eSValentin Longchamp 
55db0bb572SHolger Brunck /* architecture specific default bootargs */
56db0bb572SHolger Brunck #define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
5766072a8cSHolger Brunck 		"bootcountaddr=${bootcountaddr} ${mtdparts}"		\
5866072a8cSHolger Brunck 		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
59db0bb572SHolger Brunck 
60264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV_CPU						\
615bc0543dSMario Six 	"u-boot="CONFIG_HOSTNAME "/u-boot.kwb\0"		\
62af85f085SHolger Brunck 	CONFIG_KM_UPDATE_UBOOT						\
63b1c2a7aeSGerlando Falauto 	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
64c6d32dfdSValentin Longchamp 	"checkfdt="							\
65c6d32dfdSValentin Longchamp 		"if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; "	\
66c6d32dfdSValentin Longchamp 		"then true; else setenv cramfsloadfdt true; "		\
67c6d32dfdSValentin Longchamp 		"setenv boot bootm ${load_addr_r}; "			\
68c6d32dfdSValentin Longchamp 		"echo No FDT found, booting with the kernel "		\
69c6d32dfdSValentin Longchamp 		"appended one; fi\0"					\
70264eaa0eSValentin Longchamp 	""
71264eaa0eSValentin Longchamp 
72264eaa0eSValentin Longchamp #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
73264eaa0eSValentin Longchamp 
74264eaa0eSValentin Longchamp /*
75264eaa0eSValentin Longchamp  * NS16550 Configuration
76264eaa0eSValentin Longchamp  */
77264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL
78264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
79264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
80264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
813d3c7096SHolger Brunck #define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE
82264eaa0eSValentin Longchamp 
83264eaa0eSValentin Longchamp /*
84264eaa0eSValentin Longchamp  * Serial Port configuration
85264eaa0eSValentin Longchamp  * The following definitions let you select what serial you want to use
86264eaa0eSValentin Longchamp  * for your console driver.
87264eaa0eSValentin Longchamp  */
88264eaa0eSValentin Longchamp 
89264eaa0eSValentin Longchamp /*
90264eaa0eSValentin Longchamp  * For booting Linux, the board info and command line data
91264eaa0eSValentin Longchamp  * have to be in the first 8 MB of memory, since this is
92264eaa0eSValentin Longchamp  * the maximum mapped by the Linux kernel during initialization.
93264eaa0eSValentin Longchamp  */
94264eaa0eSValentin Longchamp #define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
95264eaa0eSValentin Longchamp #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
96264eaa0eSValentin Longchamp #define CONFIG_INITRD_TAG		/* enable INITRD tag */
97264eaa0eSValentin Longchamp #define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
98264eaa0eSValentin Longchamp 
99264eaa0eSValentin Longchamp /*
100264eaa0eSValentin Longchamp  * NAND Flash configuration
101264eaa0eSValentin Longchamp  */
102264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE	1
103264eaa0eSValentin Longchamp 
104264eaa0eSValentin Longchamp #define BOOTFLASH_START		0x0
105264eaa0eSValentin Longchamp 
1063d3c7096SHolger Brunck /* Kirkwood has two serial IF */
1073d3c7096SHolger Brunck #if (CONFIG_CONS_INDEX == 2)
1083d3c7096SHolger Brunck #define CONFIG_KM_CONSOLE_TTY	"ttyS1"
1093d3c7096SHolger Brunck #else
110264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
1113d3c7096SHolger Brunck #endif
112264eaa0eSValentin Longchamp 
113264eaa0eSValentin Longchamp /*
114264eaa0eSValentin Longchamp  * Other required minimal configurations
115264eaa0eSValentin Longchamp  */
116264eaa0eSValentin Longchamp #define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
117264eaa0eSValentin Longchamp #define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
118264eaa0eSValentin Longchamp 
119264eaa0eSValentin Longchamp /*
120264eaa0eSValentin Longchamp  * Ethernet Driver configuration
121264eaa0eSValentin Longchamp  */
122264eaa0eSValentin Longchamp #define CONFIG_NETCONSOLE	/* include NetConsole support   */
123264eaa0eSValentin Longchamp #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
124264eaa0eSValentin Longchamp #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
125264eaa0eSValentin Longchamp #define CONFIG_PHY_BASE_ADR	0
126264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
12799f6249aSValentin Longchamp #define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
128264eaa0eSValentin Longchamp 
129264eaa0eSValentin Longchamp /*
130264eaa0eSValentin Longchamp  * I2C related stuff
131264eaa0eSValentin Longchamp  */
132ea818dbbSHeiko Schocher #undef CONFIG_I2C_MVTWSI
133ea818dbbSHeiko Schocher #define CONFIG_SYS_I2C
134ea818dbbSHeiko Schocher #define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
1350a4f88b9SValentin Longchamp #define CONFIG_SYS_I2C_INIT_BOARD
136ea818dbbSHeiko Schocher 
137264eaa0eSValentin Longchamp #define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
138ea818dbbSHeiko Schocher #define CONFIG_SYS_NUM_I2C_BUSES	6
139ea818dbbSHeiko Schocher #define CONFIG_SYS_I2C_MAX_HOPS		1
140ea818dbbSHeiko Schocher #define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
141ea818dbbSHeiko Schocher 					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
142ea818dbbSHeiko Schocher 					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
143ea818dbbSHeiko Schocher 					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
144ea818dbbSHeiko Schocher 					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
145ea818dbbSHeiko Schocher 					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
146ea818dbbSHeiko Schocher 				}
147ea818dbbSHeiko Schocher 
148264eaa0eSValentin Longchamp #ifndef __ASSEMBLY__
149ea385723SMasahiro Yamada #include <asm/arch/gpio.h>
150264eaa0eSValentin Longchamp extern void __set_direction(unsigned pin, int high);
151264eaa0eSValentin Longchamp void set_sda(int state);
152264eaa0eSValentin Longchamp void set_scl(int state);
153264eaa0eSValentin Longchamp int get_sda(void);
154264eaa0eSValentin Longchamp int get_scl(void);
155264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SDA_PIN	8
156264eaa0eSValentin Longchamp #define KM_KIRKWOOD_SCL_PIN	9
157c471d848SHolger Brunck #define KM_KIRKWOOD_SOFT_I2C_GPIOS	0x0300
158264eaa0eSValentin Longchamp #define KM_KIRKWOOD_ENV_WP	38
159264eaa0eSValentin Longchamp 
160264eaa0eSValentin Longchamp #define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
161264eaa0eSValentin Longchamp #define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
162264eaa0eSValentin Longchamp #define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
163264eaa0eSValentin Longchamp #define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
164264eaa0eSValentin Longchamp #define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
165264eaa0eSValentin Longchamp #endif
166264eaa0eSValentin Longchamp 
1679e9c6d7cSHolger Brunck #define I2C_DELAY	udelay(1)
168264eaa0eSValentin Longchamp #define I2C_SOFT_DECLARATIONS
169264eaa0eSValentin Longchamp 
170ea818dbbSHeiko Schocher #define	CONFIG_SYS_I2C_SOFT_SLAVE	0x0
171ea818dbbSHeiko Schocher #define	CONFIG_SYS_I2C_SOFT_SPEED	100000
172264eaa0eSValentin Longchamp 
1734daea6ffSStefan Bigler /* EEprom support 24C128, 24C256 valid for environment eeprom */
1744daea6ffSStefan Bigler #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
1754daea6ffSStefan Bigler #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6 /* 64 Byte write page */
1764daea6ffSStefan Bigler #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
1774daea6ffSStefan Bigler 
178264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
179264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
180264eaa0eSValentin Longchamp 
181264eaa0eSValentin Longchamp /*
182264eaa0eSValentin Longchamp  *  Environment variables configurations
183264eaa0eSValentin Longchamp  */
1848170aefcSHolger Brunck #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
1858170aefcSHolger Brunck #define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
1868170aefcSHolger Brunck #define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
1878170aefcSHolger Brunck #define CONFIG_ENV_SECT_SIZE		0x10000
1888170aefcSHolger Brunck #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
1898170aefcSHolger Brunck 					CONFIG_ENV_SECT_SIZE)
1908170aefcSHolger Brunck #define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
1918170aefcSHolger Brunck #else
192264eaa0eSValentin Longchamp #define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
193264eaa0eSValentin Longchamp #define CONFIG_ENV_EEPROM_IS_ON_I2C
194264eaa0eSValentin Longchamp #define CONFIG_SYS_EEPROM_WREN
195264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
196264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
197716e4ffeSValentin Longchamp #define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
198264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
199264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
2008170aefcSHolger Brunck #endif
2018170aefcSHolger Brunck 
2028170aefcSHolger Brunck #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
203264eaa0eSValentin Longchamp 
204264eaa0eSValentin Longchamp 
2050c25defcSValentin Longchamp /* SPI bus claim MPP configuration */
2060c25defcSValentin Longchamp #define CONFIG_SYS_KW_SPI_MPP	0x0
2070c25defcSValentin Longchamp 
208264eaa0eSValentin Longchamp #define FLASH_GPIO_PIN			0x00010000
2090c25defcSValentin Longchamp #define KM_FLASH_GPIO_PIN	16
210264eaa0eSValentin Longchamp 
211af85f085SHolger Brunck #define	CONFIG_KM_UPDATE_UBOOT						\
212264eaa0eSValentin Longchamp 	"update="							\
2130c25defcSValentin Longchamp 		"sf probe 0;sf erase 0 +${filesize};"			\
2140c25defcSValentin Longchamp 		"sf write ${load_addr_r} 0 ${filesize};\0"
215264eaa0eSValentin Longchamp 
2168170aefcSHolger Brunck #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
2178170aefcSHolger Brunck #define CONFIG_KM_NEW_ENV						\
2188170aefcSHolger Brunck 	"newenv=sf probe 0;"						\
21993ea89f0SMarek Vasut 		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
22093ea89f0SMarek Vasut 		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
2218170aefcSHolger Brunck #else
2228170aefcSHolger Brunck #define CONFIG_KM_NEW_ENV						\
223ea616d4dSValentin Longchamp 	"newenv=setenv addr 0x100000 && "				\
22467bfae36SHolger Brunck 		"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; "  \
22567bfae36SHolger Brunck 		"mw.b ${addr} 0 4 && "					\
22693ea89f0SMarek Vasut 		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
22793ea89f0SMarek Vasut 		" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && "	\
22893ea89f0SMarek Vasut 		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
22993ea89f0SMarek Vasut 		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
2308170aefcSHolger Brunck #endif
2318170aefcSHolger Brunck 
23256cde177SHolger Brunck #ifndef CONFIG_KM_BOARD_EXTRA_ENV
23356cde177SHolger Brunck #define CONFIG_KM_BOARD_EXTRA_ENV       ""
23456cde177SHolger Brunck #endif
23556cde177SHolger Brunck 
2368170aefcSHolger Brunck /*
2378170aefcSHolger Brunck  * Default environment variables
2388170aefcSHolger Brunck  */
2398170aefcSHolger Brunck #define CONFIG_EXTRA_ENV_SETTINGS					\
24056cde177SHolger Brunck 	CONFIG_KM_BOARD_EXTRA_ENV					\
2418170aefcSHolger Brunck 	CONFIG_KM_DEF_ENV						\
2428170aefcSHolger Brunck 	CONFIG_KM_NEW_ENV						\
243b648bfc2SHolger Brunck 	"arch=arm\0"							\
244ea616d4dSValentin Longchamp 	""
245ea616d4dSValentin Longchamp 
246e856bdcfSMasahiro Yamada #if !defined(CONFIG_MTD_NOR_FLASH)
247264eaa0eSValentin Longchamp #undef	CONFIG_JFFS2_CMDLINE
248264eaa0eSValentin Longchamp #endif
249264eaa0eSValentin Longchamp 
250264eaa0eSValentin Longchamp /* additions for new relocation code, must be added to all boards */
251264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE		0x00000000
252264eaa0eSValentin Longchamp /* Do early setups now in board_init_f() */
253264eaa0eSValentin Longchamp 
254264eaa0eSValentin Longchamp /*
255264eaa0eSValentin Longchamp  * resereved pram area at the end of memroy [hex]
256264eaa0eSValentin Longchamp  * 8Mbytes for switch + 4Kbytes for bootcount
257264eaa0eSValentin Longchamp  */
258264eaa0eSValentin Longchamp #define CONFIG_KM_RESERVED_PRAM 0x801000
259264eaa0eSValentin Longchamp /* address for the bootcount (taken from end of RAM) */
260264eaa0eSValentin Longchamp #define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
261264eaa0eSValentin Longchamp 
2629400f8faSValentin Longchamp /* enable POST tests */
2639400f8faSValentin Longchamp #define CONFIG_POST	(CONFIG_SYS_POST_MEM_REGIONS)
2649400f8faSValentin Longchamp #define CONFIG_POST_SKIP_ENV_FLAGS
2659400f8faSValentin Longchamp #define CONFIG_POST_EXTERNAL_WORD_FUNCS
2669400f8faSValentin Longchamp 
267b37f7724SValentin Longchamp /* we do the whole PCIe FPGA config stuff here */
268b37f7724SValentin Longchamp 
269264eaa0eSValentin Longchamp #endif /* _CONFIG_KM_ARM_H */
270