1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2ebf2b9e3SZubair Lutfullah Kakakhel /* 3ebf2b9e3SZubair Lutfullah Kakakhel * Copyright (C) 2016, Imagination Technologies Ltd. 4ebf2b9e3SZubair Lutfullah Kakakhel * 5ebf2b9e3SZubair Lutfullah Kakakhel * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> 6ebf2b9e3SZubair Lutfullah Kakakhel * 7ebf2b9e3SZubair Lutfullah Kakakhel * Imagination Technologies Ltd. MIPSfpga 8ebf2b9e3SZubair Lutfullah Kakakhel */ 9ebf2b9e3SZubair Lutfullah Kakakhel 10ebf2b9e3SZubair Lutfullah Kakakhel #ifndef __XILFPGA_CONFIG_H 11ebf2b9e3SZubair Lutfullah Kakakhel #define __XILFPGA_CONFIG_H 12ebf2b9e3SZubair Lutfullah Kakakhel 13ebf2b9e3SZubair Lutfullah Kakakhel /* BootROM + MIG is pretty smart. DDR and Cache initialized */ 14ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SKIP_LOWLEVEL_INIT 15ebf2b9e3SZubair Lutfullah Kakakhel 16ebf2b9e3SZubair Lutfullah Kakakhel /*-------------------------------------------- 17ebf2b9e3SZubair Lutfullah Kakakhel * CPU configuration 18ebf2b9e3SZubair Lutfullah Kakakhel */ 19ebf2b9e3SZubair Lutfullah Kakakhel /* CPU Timer rate */ 20ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 21ebf2b9e3SZubair Lutfullah Kakakhel 22ebf2b9e3SZubair Lutfullah Kakakhel /*---------------------------------------------------------------------- 23ebf2b9e3SZubair Lutfullah Kakakhel * Memory Layout 24ebf2b9e3SZubair Lutfullah Kakakhel */ 25ebf2b9e3SZubair Lutfullah Kakakhel 26ebf2b9e3SZubair Lutfullah Kakakhel /* SDRAM Configuration (for final code, data, stack, heap) */ 27ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_SDRAM_BASE 0x80000000 28ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ 29ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_INIT_SP_ADDR \ 30ebf2b9e3SZubair Lutfullah Kakakhel (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) 31ebf2b9e3SZubair Lutfullah Kakakhel 32ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_MALLOC_LEN (256 << 10) 33ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 34ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ 35ebf2b9e3SZubair Lutfullah Kakakhel 36ebf2b9e3SZubair Lutfullah Kakakhel /*---------------------------------------------------------------------- 37ebf2b9e3SZubair Lutfullah Kakakhel * Commands 38ebf2b9e3SZubair Lutfullah Kakakhel */ 39ebf2b9e3SZubair Lutfullah Kakakhel 40ebf2b9e3SZubair Lutfullah Kakakhel /*------------------------------------------------------------ 41ebf2b9e3SZubair Lutfullah Kakakhel * Console Configuration 42ebf2b9e3SZubair Lutfullah Kakakhel */ 43ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 44ebf2b9e3SZubair Lutfullah Kakakhel 45ebf2b9e3SZubair Lutfullah Kakakhel /* ------------------------------------------------- 46ebf2b9e3SZubair Lutfullah Kakakhel * Environment 47ebf2b9e3SZubair Lutfullah Kakakhel */ 48ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_ENV_SIZE 0x4000 49ebf2b9e3SZubair Lutfullah Kakakhel 50ebf2b9e3SZubair Lutfullah Kakakhel /* --------------------------------------------------------------------- 51ebf2b9e3SZubair Lutfullah Kakakhel * Board boot configuration 52ebf2b9e3SZubair Lutfullah Kakakhel */ 53ebf2b9e3SZubair Lutfullah Kakakhel #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 54ebf2b9e3SZubair Lutfullah Kakakhel 55ebf2b9e3SZubair Lutfullah Kakakhel #endif /* __XILFPGA_CONFIG_H */ 56