1 /* 2 * Copyright (C) 2013 Samsung Electronics 3 * 4 * Configuration settings for the SAMSUNG EXYNOS5 board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_EXYNOS5_COMMON_H 10 #define __CONFIG_EXYNOS5_COMMON_H 11 12 #define CONFIG_EXYNOS5 /* Exynos5 Family */ 13 14 #include "exynos-common.h" 15 16 #define CONFIG_EXYNOS_SPL 17 18 #ifdef FTRACE 19 #define CONFIG_TRACE 20 #define CONFIG_CMD_TRACE 21 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) 22 #define CONFIG_TRACE_EARLY_SIZE (8 << 20) 23 #define CONFIG_TRACE_EARLY 24 #define CONFIG_TRACE_EARLY_ADDR 0x50000000 25 #endif 26 27 /* Enable ACE acceleration for SHA1 and SHA256 */ 28 #define CONFIG_EXYNOS_ACE_SHA 29 30 /* Power Down Modes */ 31 #define S5P_CHECK_SLEEP 0x00000BAD 32 #define S5P_CHECK_DIDLE 0xBAD00000 33 #define S5P_CHECK_LPA 0xABAD0000 34 35 /* Offset for inform registers */ 36 #define INFORM0_OFFSET 0x800 37 #define INFORM1_OFFSET 0x804 38 #define INFORM2_OFFSET 0x808 39 #define INFORM3_OFFSET 0x80c 40 41 /* select serial console configuration */ 42 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 43 44 #define CONFIG_CMD_HASH 45 46 /* Thermal Management Unit */ 47 #define CONFIG_EXYNOS_TMU 48 49 /* MMC SPL */ 50 #define COPY_BL2_FNPTR_ADDR 0x02020030 51 #define CONFIG_SUPPORT_EMMC_BOOT 52 53 /* specific .lds file */ 54 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" 55 56 /* Boot Argument Buffer Size */ 57 /* memtest works on */ 58 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 59 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) 60 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 61 62 #define CONFIG_RD_LVL 63 64 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 65 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 66 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 67 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 68 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 69 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 70 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 71 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 72 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 73 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 74 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 75 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 76 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 77 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 78 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 79 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 80 81 #define CONFIG_SYS_MONITOR_BASE 0x00000000 82 83 #define CONFIG_SYS_MMC_ENV_DEV 0 84 85 #define CONFIG_SECURE_BL1_ONLY 86 87 /* Secure FW size configuration */ 88 #ifdef CONFIG_SECURE_BL1_ONLY 89 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ 90 #else 91 #define CONFIG_SEC_FW_SIZE 0 92 #endif 93 94 /* Configuration of BL1, BL2, ENV Blocks on mmc */ 95 #define CONFIG_RES_BLOCK_SIZE (512) 96 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 97 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ 98 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 99 100 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) 101 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) 102 103 /* U-Boot copy size from boot Media to DRAM.*/ 104 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) 105 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) 106 107 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 108 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) 109 110 /* I2C */ 111 #define CONFIG_SYS_I2C_S3C24X0 112 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ 113 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 114 115 /* SPI */ 116 #ifdef CONFIG_SPI_FLASH 117 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 118 #define CONFIG_SF_DEFAULT_SPEED 50000000 119 #endif 120 121 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 122 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 123 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 124 #define CONFIG_ENV_SPI_BUS 1 125 #define CONFIG_ENV_SPI_MAX_HZ 50000000 126 #endif 127 128 /* Ethernet Controllor Driver */ 129 #ifdef CONFIG_CMD_NET 130 #define CONFIG_SMC911X 131 #define CONFIG_SMC911X_BASE 0x5000000 132 #define CONFIG_SMC911X_16_BIT 133 #define CONFIG_ENV_SROM_BANK 1 134 #endif /*CONFIG_CMD_NET*/ 135 136 /* SHA hashing */ 137 #define CONFIG_CMD_HASH 138 #define CONFIG_HASH_VERIFY 139 140 /* Enable Time Command */ 141 142 /* USB */ 143 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 144 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 145 146 #define CONFIG_USB_HOST_ETHER 147 #define CONFIG_USB_ETHER_ASIX 148 #define CONFIG_USB_ETHER_SMSC95XX 149 #define CONFIG_USB_ETHER_RTL8152 150 151 /* USB boot mode */ 152 #define CONFIG_USB_BOOTING 153 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 154 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 155 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 156 157 #define BOOT_TARGET_DEVICES(func) \ 158 func(MMC, mmc, 1) \ 159 func(MMC, mmc, 0) \ 160 func(PXE, pxe, na) \ 161 func(DHCP, dhcp, na) 162 163 #include <config_distro_bootcmd.h> 164 165 #ifndef MEM_LAYOUT_ENV_SETTINGS 166 /* 2GB RAM, bootm size of 256M, load scripts after that */ 167 #define MEM_LAYOUT_ENV_SETTINGS \ 168 "bootm_size=0x10000000\0" \ 169 "kernel_addr_r=0x42000000\0" \ 170 "fdt_addr_r=0x43000000\0" \ 171 "ramdisk_addr_r=0x43300000\0" \ 172 "scriptaddr=0x50000000\0" \ 173 "pxefile_addr_r=0x51000000\0" 174 #endif 175 176 #ifndef EXYNOS_DEVICE_SETTINGS 177 #define EXYNOS_DEVICE_SETTINGS \ 178 "stdin=serial\0" \ 179 "stdout=serial\0" \ 180 "stderr=serial\0" 181 #endif 182 183 #ifndef EXYNOS_FDTFILE_SETTING 184 #define EXYNOS_FDTFILE_SETTING 185 #endif 186 187 #define CONFIG_EXTRA_ENV_SETTINGS \ 188 EXYNOS_DEVICE_SETTINGS \ 189 EXYNOS_FDTFILE_SETTING \ 190 MEM_LAYOUT_ENV_SETTINGS \ 191 BOOTENV 192 193 #endif /* __CONFIG_EXYNOS5_COMMON_H */ 194