1 /* 2 * DHCOM DH-iMX6 PDK board configuration 3 * 4 * Copyright (C) 2017 Marek Vasut <marex@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __DH_IMX6_CONFIG_H 10 #define __DH_IMX6_CONFIG_H 11 12 #include <asm/arch/imx-regs.h> 13 14 #include <config_distro_defaults.h> 15 #include "mx6_common.h" 16 17 /* 18 * SPI NOR layout: 19 * 0x00_0000-0x00_ffff ... U-Boot SPL 20 * 0x01_0000-0x0f_ffff ... U-Boot 21 * 0x10_0000-0x10_ffff ... U-Boot env #1 22 * 0x11_0000-0x11_ffff ... U-Boot env #2 23 * 0x12_0000-0x1f_ffff ... UNUSED 24 */ 25 26 /* SPL */ 27 #include "imx6_spl.h" /* common IMX6 SPL configuration */ 28 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 29 #define CONFIG_SPL_SPI_LOAD 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" 31 32 /* Miscellaneous configurable options */ 33 #define CONFIG_SYS_LONGHELP 34 #define CONFIG_AUTO_COMPLETE 35 #define CONFIG_CMDLINE_EDITING 36 37 #define CONFIG_CMDLINE_TAG 38 #define CONFIG_SETUP_MEMORY_TAGS 39 #define CONFIG_INITRD_TAG 40 #define CONFIG_REVISION_TAG 41 42 #define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */ 43 #define CONFIG_BOUNCE_BUFFER 44 #define CONFIG_BZIP2 45 46 /* Size of malloc() pool */ 47 #define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) 48 49 /* Bootcounter */ 50 #define CONFIG_BOOTCOUNT_LIMIT 51 #define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR 52 #define CONFIG_SYS_BOOTCOUNT_BE 53 54 /* FEC ethernet */ 55 #define CONFIG_MII 56 #define IMX_FEC_BASE ENET_BASE_ADDR 57 #define CONFIG_FEC_XCV_TYPE RMII 58 #define CONFIG_ETHPRIME "FEC" 59 #define CONFIG_FEC_MXC_PHYADDR 0 60 #define CONFIG_ARP_TIMEOUT 200UL 61 62 /* Fuses */ 63 #ifdef CONFIG_CMD_FUSE 64 #define CONFIG_MXC_OCOTP 65 #endif 66 67 /* I2C Configs */ 68 #define CONFIG_SYS_I2C 69 #define CONFIG_SYS_I2C_MXC 70 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 71 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 72 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 73 #define CONFIG_SYS_I2C_SPEED 100000 74 75 /* MMC Configs */ 76 #define CONFIG_FSL_ESDHC 77 #define CONFIG_FSL_USDHC 78 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 79 #define CONFIG_SYS_FSL_USDHC_NUM 3 80 #define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ 81 82 /* SATA Configs */ 83 #ifdef CONFIG_CMD_SATA 84 #define CONFIG_SYS_SATA_MAX_DEVICE 1 85 #define CONFIG_DWC_AHSATA_PORT_ID 0 86 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 87 #define CONFIG_LBA48 88 #endif 89 90 /* SPI Flash Configs */ 91 #ifdef CONFIG_CMD_SF 92 #define CONFIG_SF_DEFAULT_BUS 0 93 #define CONFIG_SF_DEFAULT_CS 0 94 #define CONFIG_SF_DEFAULT_SPEED 25000000 95 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 96 #endif 97 98 /* UART */ 99 #define CONFIG_MXC_UART 100 #define CONFIG_MXC_UART_BASE UART1_BASE 101 #define CONFIG_CONS_INDEX 1 102 #define CONFIG_BAUDRATE 115200 103 104 /* USB Configs */ 105 #ifdef CONFIG_CMD_USB 106 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 107 #define CONFIG_USB_HOST_ETHER 108 #define CONFIG_USB_ETHER_ASIX 109 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 110 #define CONFIG_MXC_USB_FLAGS 0 111 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ 112 113 /* USB Gadget (DFU, UMS) */ 114 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 115 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 116 #define DFU_DEFAULT_POLL_TIMEOUT 300 117 118 /* USB IDs */ 119 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 120 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 121 #endif 122 #endif 123 124 /* Watchdog */ 125 #define CONFIG_HW_WATCHDOG 126 #define CONFIG_IMX_WATCHDOG 127 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 128 129 /* allow to overwrite serial and ethaddr */ 130 #define CONFIG_ENV_OVERWRITE 131 132 #define CONFIG_LOADADDR 0x12000000 133 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 134 135 #ifndef CONFIG_SPL_BUILD 136 #define CONFIG_EXTRA_ENV_SETTINGS \ 137 "console=ttymxc0,115200\0" \ 138 "fdt_addr=0x18000000\0" \ 139 "fdt_high=0xffffffff\0" \ 140 "initrd_high=0xffffffff\0" \ 141 "kernel_addr_r=0x10008000\0" \ 142 "fdt_addr_r=0x13000000\0" \ 143 "ramdisk_addr_r=0x18000000\0" \ 144 "scriptaddr=0x14000000\0" \ 145 "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ 146 BOOTENV 147 148 #define CONFIG_BOOTCOMMAND "run distro_bootcmd" 149 150 #define BOOT_TARGET_DEVICES(func) \ 151 func(MMC, mmc, 0) \ 152 func(MMC, mmc, 2) \ 153 func(USB, usb, 1) \ 154 func(SATA, sata, 0) \ 155 func(DHCP, dhcp, na) 156 157 #include <config_distro_bootcmd.h> 158 #endif 159 160 /* Physical Memory Map */ 161 #define CONFIG_NR_DRAM_BANKS 1 162 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 163 164 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 165 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 166 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 167 168 #define CONFIG_SYS_INIT_SP_OFFSET \ 169 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 170 171 #define CONFIG_SYS_INIT_SP_ADDR \ 172 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 173 174 #define CONFIG_SYS_MEMTEST_START 0x10000000 175 #define CONFIG_SYS_MEMTEST_END 0x20000000 176 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 177 178 /* Environment */ 179 #define CONFIG_ENV_SIZE (16 * 1024) 180 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 181 182 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 183 #define CONFIG_ENV_OFFSET (1024 * 1024) 184 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 185 #define CONFIG_ENV_OFFSET_REDUND \ 186 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 187 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 188 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 189 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 190 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 191 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 192 #endif 193 194 #endif /* __DH_IMX6_CONFIG_H */ 195