1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 /* check if direct NOR boot config is used */ 19 #ifndef CONFIG_DIRECT_NOR_BOOT 20 #define CONFIG_USE_SPIFLASH 21 #endif 22 23 /* 24 * Disable DM_* for SPL build and can be re-enabled after adding 25 * DM support in SPL 26 */ 27 #ifdef CONFIG_SPL_BUILD 28 #undef CONFIG_DM_SPI 29 #undef CONFIG_DM_SPI_FLASH 30 #undef CONFIG_DM_I2C 31 #undef CONFIG_DM_I2C_COMPAT 32 #endif 33 /* 34 * SoC Configuration 35 */ 36 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 37 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 38 #define CONFIG_SYS_OSCIN_FREQ 24000000 39 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 40 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 41 42 #ifdef CONFIG_DIRECT_NOR_BOOT 43 #define CONFIG_ARCH_CPU_INIT 44 #define CONFIG_DA8XX_GPIO 45 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 46 #endif 47 48 /* 49 * Memory Info 50 */ 51 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 52 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 53 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 54 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 55 56 /* memtest start addr */ 57 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 58 59 /* memtest will be run on 16MB */ 60 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 61 62 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 63 64 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 65 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 66 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 67 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 68 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 69 DAVINCI_SYSCFG_SUSPSRC_I2C) 70 71 /* 72 * PLL configuration 73 */ 74 75 #define CONFIG_SYS_DA850_PLL0_PLLM 24 76 #define CONFIG_SYS_DA850_PLL1_PLLM 21 77 78 /* 79 * DDR2 memory configuration 80 */ 81 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 82 DV_DDR_PHY_EXT_STRBEN | \ 83 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 84 85 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 86 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 87 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 88 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 89 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 90 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 91 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 92 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 93 94 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 95 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 96 97 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 98 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 99 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 100 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 101 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 102 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 103 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 104 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 105 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 106 107 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 108 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 109 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 110 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 111 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 112 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 113 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 114 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 115 116 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 117 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 118 119 /* 120 * Serial Driver info 121 */ 122 123 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT) 124 #define CONFIG_SYS_NS16550_SERIAL 125 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 126 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 127 #endif 128 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 129 130 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 131 #ifdef CONFIG_SPL_BUILD 132 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 133 #define CONFIG_SF_DEFAULT_SPEED 30000000 134 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 135 #endif 136 137 #ifdef CONFIG_USE_SPIFLASH 138 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 139 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 140 #endif 141 142 /* 143 * I2C Configuration 144 */ 145 #ifndef CONFIG_SPL_BUILD 146 #define CONFIG_SYS_I2C_DAVINCI 147 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 148 #endif 149 150 /* 151 * Flash & Environment 152 */ 153 #ifdef CONFIG_USE_NAND 154 #define CONFIG_NAND_DAVINCI 155 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 156 #define CONFIG_ENV_SIZE (128 << 10) 157 #define CONFIG_SYS_NAND_USE_FLASH_BBT 158 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 159 #define CONFIG_SYS_NAND_PAGE_2K 160 #define CONFIG_SYS_NAND_CS 3 161 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 162 #define CONFIG_SYS_NAND_MASK_CLE 0x10 163 #define CONFIG_SYS_NAND_MASK_ALE 0x8 164 #undef CONFIG_SYS_NAND_HW_ECC 165 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 166 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 167 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 168 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 169 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 170 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 171 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 172 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 173 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 174 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 175 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 176 CONFIG_SYS_MALLOC_LEN - \ 177 GENERATED_GBL_DATA_SIZE) 178 #define CONFIG_SYS_NAND_ECCPOS { \ 179 24, 25, 26, 27, 28, \ 180 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 181 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 182 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 183 59, 60, 61, 62, 63 } 184 #define CONFIG_SYS_NAND_PAGE_COUNT 64 185 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 186 #define CONFIG_SYS_NAND_ECCSIZE 512 187 #define CONFIG_SYS_NAND_ECCBYTES 10 188 #define CONFIG_SYS_NAND_OOBSIZE 64 189 #define CONFIG_SPL_NAND_BASE 190 #define CONFIG_SPL_NAND_DRIVERS 191 #define CONFIG_SPL_NAND_ECC 192 #define CONFIG_SPL_NAND_LOAD 193 #endif 194 195 /* 196 * Network & Ethernet Configuration 197 */ 198 #ifdef CONFIG_DRIVER_TI_EMAC 199 #define CONFIG_MII 200 #define CONFIG_BOOTP_DNS2 201 #define CONFIG_BOOTP_SEND_HOSTNAME 202 #define CONFIG_NET_RETRY_COUNT 10 203 #endif 204 205 #ifdef CONFIG_USE_NOR 206 #define CONFIG_FLASH_CFI_DRIVER 207 #define CONFIG_SYS_FLASH_CFI 208 #define CONFIG_SYS_FLASH_PROTECTION 209 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 210 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 211 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 212 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 213 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 214 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 215 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 216 + 3) 217 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 218 #endif 219 220 #ifdef CONFIG_USE_SPIFLASH 221 #define CONFIG_ENV_SIZE (64 << 10) 222 #define CONFIG_ENV_OFFSET (512 << 10) 223 #define CONFIG_ENV_SECT_SIZE (64 << 10) 224 #ifdef CONFIG_SPL_BUILD 225 #undef CONFIG_SPI_FLASH_MTD 226 #endif 227 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 228 #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ 229 #endif 230 231 /* 232 * U-Boot general configuration 233 */ 234 #define CONFIG_MISC_INIT_R 235 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 236 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 237 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 238 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 239 #define CONFIG_MX_CYCLIC 240 241 /* 242 * Linux Information 243 */ 244 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 245 #define CONFIG_HWCONFIG /* enable hwconfig */ 246 #define CONFIG_CMDLINE_TAG 247 #define CONFIG_REVISION_TAG 248 #define CONFIG_SETUP_MEMORY_TAGS 249 250 #define CONFIG_BOOTCOMMAND \ 251 "run envboot; " \ 252 "run mmcboot; " 253 254 #define DEFAULT_LINUX_BOOT_ENV \ 255 "loadaddr=0xc0700000\0" \ 256 "fdtaddr=0xc0600000\0" \ 257 "scriptaddr=0xc0600000\0" 258 259 #include <environment/ti/mmc.h> 260 261 #define CONFIG_EXTRA_ENV_SETTINGS \ 262 DEFAULT_LINUX_BOOT_ENV \ 263 DEFAULT_MMC_TI_ARGS \ 264 "bootpart=0:2\0" \ 265 "bootdir=/boot\0" \ 266 "bootfile=zImage\0" \ 267 "fdtfile=da850-evm.dtb\0" \ 268 "boot_fdt=yes\0" \ 269 "boot_fit=0\0" \ 270 "console=ttyS2,115200n8\0" \ 271 "hwconfig=dsp:wake=yes" 272 273 #ifdef CONFIG_CMD_BDI 274 #define CONFIG_CLOCKS 275 #endif 276 277 #ifdef CONFIG_USE_NAND 278 #define CONFIG_MTD_DEVICE 279 #define CONFIG_MTD_PARTITIONS 280 #endif 281 282 #if !defined(CONFIG_USE_NAND) && \ 283 !defined(CONFIG_USE_NOR) && \ 284 !defined(CONFIG_USE_SPIFLASH) 285 #define CONFIG_ENV_SIZE (16 << 10) 286 #endif 287 288 #ifndef CONFIG_DIRECT_NOR_BOOT 289 /* defines for SPL */ 290 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 291 CONFIG_SYS_MALLOC_LEN) 292 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 293 #define CONFIG_SPL_STACK 0x8001ff00 294 #define CONFIG_SPL_TEXT_BASE 0x80000000 295 #define CONFIG_SPL_MAX_FOOTPRINT 32768 296 #define CONFIG_SPL_PAD_TO 32768 297 #endif 298 299 /* Load U-Boot Image From MMC */ 300 301 /* additions for new relocation code, must added to all boards */ 302 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 303 304 #ifdef CONFIG_DIRECT_NOR_BOOT 305 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 306 #else 307 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 308 GENERATED_GBL_DATA_SIZE) 309 #endif /* CONFIG_DIRECT_NOR_BOOT */ 310 311 #include <asm/arch/hardware.h> 312 313 #endif /* __CONFIG_H */ 314