1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on davinci_dvevm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * Board 16 */ 17 #define CONFIG_DRIVER_TI_EMAC 18 /* check if direct NOR boot config is used */ 19 #ifndef CONFIG_DIRECT_NOR_BOOT 20 #define CONFIG_USE_SPIFLASH 21 #endif 22 23 /* 24 * Disable DM_* for SPL build and can be re-enabled after adding 25 * DM support in SPL 26 */ 27 #ifdef CONFIG_SPL_BUILD 28 #undef CONFIG_DM_SPI 29 #undef CONFIG_DM_SPI_FLASH 30 #undef CONFIG_DM_I2C 31 #undef CONFIG_DM_I2C_COMPAT 32 #endif 33 /* 34 * SoC Configuration 35 */ 36 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 37 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 38 #define CONFIG_SYS_OSCIN_FREQ 24000000 39 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 40 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 41 42 #ifdef CONFIG_DIRECT_NOR_BOOT 43 #define CONFIG_ARCH_CPU_INIT 44 #define CONFIG_DA8XX_GPIO 45 #define CONFIG_SYS_TEXT_BASE 0x60000000 46 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 47 #else 48 #define CONFIG_SYS_TEXT_BASE 0xc1080000 49 #endif 50 51 /* 52 * Memory Info 53 */ 54 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 55 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 56 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 57 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 58 59 /* memtest start addr */ 60 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 61 62 /* memtest will be run on 16MB */ 63 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 64 65 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 66 67 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 68 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 69 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 70 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 71 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 72 DAVINCI_SYSCFG_SUSPSRC_I2C) 73 74 /* 75 * PLL configuration 76 */ 77 78 #define CONFIG_SYS_DA850_PLL0_PLLM 24 79 #define CONFIG_SYS_DA850_PLL1_PLLM 21 80 81 /* 82 * DDR2 memory configuration 83 */ 84 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 85 DV_DDR_PHY_EXT_STRBEN | \ 86 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 87 88 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 89 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 90 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 91 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 92 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 93 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 94 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 95 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 96 97 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 98 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 99 100 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 101 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 102 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 103 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 104 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 105 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 106 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 107 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 108 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 109 110 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 111 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 112 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 113 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 114 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 115 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 116 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 117 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 118 119 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 120 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 121 122 /* 123 * Serial Driver info 124 */ 125 126 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT) 127 #define CONFIG_SYS_NS16550_SERIAL 128 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 129 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 130 #endif 131 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 132 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 133 134 #define CONFIG_SPI 135 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 136 #ifdef CONFIG_SPL_BUILD 137 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 138 #define CONFIG_SF_DEFAULT_SPEED 30000000 139 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 140 #endif 141 142 #ifdef CONFIG_USE_SPIFLASH 143 #define CONFIG_SPL_SPI_LOAD 144 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 145 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 146 #endif 147 148 /* 149 * I2C Configuration 150 */ 151 #ifndef CONFIG_SPL_BUILD 152 #define CONFIG_SYS_I2C_DAVINCI 153 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 154 #endif 155 156 /* 157 * Flash & Environment 158 */ 159 #ifdef CONFIG_USE_NAND 160 #define CONFIG_NAND_DAVINCI 161 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 162 #define CONFIG_ENV_SIZE (128 << 10) 163 #define CONFIG_SYS_NAND_USE_FLASH_BBT 164 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 165 #define CONFIG_SYS_NAND_PAGE_2K 166 #define CONFIG_SYS_NAND_CS 3 167 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 168 #define CONFIG_SYS_NAND_MASK_CLE 0x10 169 #define CONFIG_SYS_NAND_MASK_ALE 0x8 170 #undef CONFIG_SYS_NAND_HW_ECC 171 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 172 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 173 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 174 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 175 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 176 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 177 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 178 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 179 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 180 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 181 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 182 CONFIG_SYS_MALLOC_LEN - \ 183 GENERATED_GBL_DATA_SIZE) 184 #define CONFIG_SYS_NAND_ECCPOS { \ 185 24, 25, 26, 27, 28, \ 186 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 187 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 188 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 189 59, 60, 61, 62, 63 } 190 #define CONFIG_SYS_NAND_PAGE_COUNT 64 191 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 192 #define CONFIG_SYS_NAND_ECCSIZE 512 193 #define CONFIG_SYS_NAND_ECCBYTES 10 194 #define CONFIG_SYS_NAND_OOBSIZE 64 195 #define CONFIG_SPL_NAND_BASE 196 #define CONFIG_SPL_NAND_DRIVERS 197 #define CONFIG_SPL_NAND_ECC 198 #define CONFIG_SPL_NAND_LOAD 199 #endif 200 201 /* 202 * Network & Ethernet Configuration 203 */ 204 #ifdef CONFIG_DRIVER_TI_EMAC 205 #define CONFIG_MII 206 #define CONFIG_BOOTP_DNS 207 #define CONFIG_BOOTP_DNS2 208 #define CONFIG_BOOTP_SEND_HOSTNAME 209 #define CONFIG_NET_RETRY_COUNT 10 210 #endif 211 212 #ifdef CONFIG_USE_NOR 213 #define CONFIG_FLASH_CFI_DRIVER 214 #define CONFIG_SYS_FLASH_CFI 215 #define CONFIG_SYS_FLASH_PROTECTION 216 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 217 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 218 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) 219 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ 220 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 221 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ 222 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ 223 + 3) 224 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 225 #endif 226 227 #ifdef CONFIG_USE_SPIFLASH 228 #define CONFIG_ENV_SIZE (64 << 10) 229 #define CONFIG_ENV_OFFSET (512 << 10) 230 #define CONFIG_ENV_SECT_SIZE (64 << 10) 231 #ifdef CONFIG_SPL_BUILD 232 #undef CONFIG_SPI_FLASH_MTD 233 #endif 234 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 235 #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ 236 #endif 237 238 /* 239 * U-Boot general configuration 240 */ 241 #define CONFIG_MISC_INIT_R 242 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 243 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 244 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 245 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 246 #define CONFIG_AUTO_COMPLETE 247 #define CONFIG_CMDLINE_EDITING 248 #define CONFIG_SYS_LONGHELP 249 #define CONFIG_MX_CYCLIC 250 251 /* 252 * Linux Information 253 */ 254 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 255 #define CONFIG_HWCONFIG /* enable hwconfig */ 256 #define CONFIG_CMDLINE_TAG 257 #define CONFIG_REVISION_TAG 258 #define CONFIG_SETUP_MEMORY_TAGS 259 260 #define CONFIG_BOOTCOMMAND \ 261 "run envboot; " \ 262 "run mmcboot; " 263 264 #define DEFAULT_LINUX_BOOT_ENV \ 265 "loadaddr=0xc0700000\0" \ 266 "fdtaddr=0xc0600000\0" \ 267 "scriptaddr=0xc0600000\0" 268 269 #include <environment/ti/mmc.h> 270 271 #define CONFIG_EXTRA_ENV_SETTINGS \ 272 DEFAULT_LINUX_BOOT_ENV \ 273 DEFAULT_MMC_TI_ARGS \ 274 "bootpart=0:2\0" \ 275 "bootdir=/boot\0" \ 276 "bootfile=zImage\0" \ 277 "fdtfile=da850-evm.dtb\0" \ 278 "boot_fdt=yes\0" \ 279 "boot_fit=0\0" \ 280 "console=ttyS2,115200n8\0" \ 281 "hwconfig=dsp:wake=yes" 282 283 #ifdef CONFIG_CMD_BDI 284 #define CONFIG_CLOCKS 285 #endif 286 287 #ifdef CONFIG_USE_NAND 288 #define CONFIG_MTD_DEVICE 289 #define CONFIG_MTD_PARTITIONS 290 #endif 291 292 #if !defined(CONFIG_USE_NAND) && \ 293 !defined(CONFIG_USE_NOR) && \ 294 !defined(CONFIG_USE_SPIFLASH) 295 #define CONFIG_ENV_SIZE (16 << 10) 296 #endif 297 298 #ifndef CONFIG_DIRECT_NOR_BOOT 299 /* defines for SPL */ 300 #define CONFIG_SPL_FRAMEWORK 301 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 302 CONFIG_SYS_MALLOC_LEN) 303 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 304 #define CONFIG_SPL_SPI_LOAD 305 #define CONFIG_SPL_STACK 0x8001ff00 306 #define CONFIG_SPL_TEXT_BASE 0x80000000 307 #define CONFIG_SPL_MAX_FOOTPRINT 32768 308 #define CONFIG_SPL_PAD_TO 32768 309 #endif 310 311 /* Load U-Boot Image From MMC */ 312 #ifdef CONFIG_SPL_MMC_LOAD 313 #undef CONFIG_SPL_SPI_LOAD 314 #endif 315 316 /* additions for new relocation code, must added to all boards */ 317 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 318 319 #ifdef CONFIG_DIRECT_NOR_BOOT 320 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 321 #else 322 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 323 GENERATED_GBL_DATA_SIZE) 324 #endif /* CONFIG_DIRECT_NOR_BOOT */ 325 326 #include <asm/arch/hardware.h> 327 328 #endif /* __CONFIG_H */ 329