1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 57 #define CONFIG_PCIE1 /* PCIE controller 1 */ 58 #define CONFIG_PCIE2 /* PCIE controller 2 */ 59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 61 62 #define CONFIG_ENV_OVERWRITE 63 64 #ifndef CONFIG_MTD_NOR_FLASH 65 #else 66 #define CONFIG_FLASH_CFI_DRIVER 67 #define CONFIG_SYS_FLASH_CFI 68 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 69 #endif 70 71 #if defined(CONFIG_SPIFLASH) 72 #define CONFIG_SYS_EXTRA_ENV_RELOC 73 #define CONFIG_ENV_SPI_BUS 0 74 #define CONFIG_ENV_SPI_CS 0 75 #define CONFIG_ENV_SPI_MAX_HZ 10000000 76 #define CONFIG_ENV_SPI_MODE 0 77 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 78 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 79 #define CONFIG_ENV_SECT_SIZE 0x10000 80 #elif defined(CONFIG_SDCARD) 81 #define CONFIG_SYS_EXTRA_ENV_RELOC 82 #define CONFIG_FSL_FIXED_MMC_LOCATION 83 #define CONFIG_SYS_MMC_ENV_DEV 0 84 #define CONFIG_ENV_SIZE 0x2000 85 #define CONFIG_ENV_OFFSET (512 * 1658) 86 #elif defined(CONFIG_NAND) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 89 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 90 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 91 #define CONFIG_ENV_ADDR 0xffe20000 92 #define CONFIG_ENV_SIZE 0x2000 93 #elif defined(CONFIG_ENV_IS_NOWHERE) 94 #define CONFIG_ENV_SIZE 0x2000 95 #else 96 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 97 #define CONFIG_ENV_SIZE 0x2000 98 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 99 #endif 100 101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 102 103 /* 104 * These can be toggled for performance analysis, otherwise use default. 105 */ 106 #define CONFIG_SYS_CACHE_STASHING 107 #define CONFIG_BACKSIDE_L2_CACHE 108 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 109 #define CONFIG_BTB /* toggle branch predition */ 110 #define CONFIG_DDR_ECC 111 #ifdef CONFIG_DDR_ECC 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 114 #endif 115 116 #define CONFIG_ENABLE_36BIT_PHYS 117 118 #ifdef CONFIG_PHYS_64BIT 119 #define CONFIG_ADDR_MAP 120 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 121 #endif 122 123 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 124 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 125 #define CONFIG_SYS_MEMTEST_END 0x00400000 126 127 /* 128 * Config the L3 Cache as L3 SRAM 129 */ 130 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 133 #else 134 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 135 #endif 136 #define CONFIG_SYS_L3_SIZE (1024 << 10) 137 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 138 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SYS_DCSRBAR 0xf0000000 141 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 142 #endif 143 144 /* EEPROM */ 145 #define CONFIG_ID_EEPROM 146 #define CONFIG_SYS_I2C_EEPROM_NXID 147 #define CONFIG_SYS_EEPROM_BUS_NUM 0 148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 150 151 /* 152 * DDR Setup 153 */ 154 #define CONFIG_VERY_BIG_RAM 155 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 156 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 157 158 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 159 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 160 161 #define CONFIG_DDR_SPD 162 163 #define CONFIG_SYS_SPD_BUS_NUM 1 164 #define SPD_EEPROM_ADDRESS1 0x51 165 #define SPD_EEPROM_ADDRESS2 0x52 166 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 167 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 168 169 /* 170 * Local Bus Definitions 171 */ 172 173 /* Set the local bus clock 1/8 of platform clock */ 174 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 175 176 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 177 #ifdef CONFIG_PHYS_64BIT 178 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 179 #else 180 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 181 #endif 182 183 #define CONFIG_SYS_FLASH_BR_PRELIM \ 184 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 185 | BR_PS_16 | BR_V) 186 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 187 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 188 189 #define CONFIG_SYS_BR1_PRELIM \ 190 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 191 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 192 193 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define PIXIS_BASE_PHYS 0xfffdf0000ull 196 #else 197 #define PIXIS_BASE_PHYS PIXIS_BASE 198 #endif 199 200 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 201 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 202 203 #define PIXIS_LBMAP_SWITCH 7 204 #define PIXIS_LBMAP_MASK 0xf0 205 #define PIXIS_LBMAP_SHIFT 4 206 #define PIXIS_LBMAP_ALTBANK 0x40 207 208 #define CONFIG_SYS_FLASH_QUIET_TEST 209 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 210 211 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 213 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 215 216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 217 218 #if defined(CONFIG_RAMBOOT_PBL) 219 #define CONFIG_SYS_RAMBOOT 220 #endif 221 222 /* Nand Flash */ 223 #ifdef CONFIG_NAND_FSL_ELBC 224 #define CONFIG_SYS_NAND_BASE 0xffa00000 225 #ifdef CONFIG_PHYS_64BIT 226 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 227 #else 228 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 229 #endif 230 231 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 232 #define CONFIG_SYS_MAX_NAND_DEVICE 1 233 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 234 235 /* NAND flash config */ 236 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 237 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 238 | BR_PS_8 /* Port Size = 8 bit */ \ 239 | BR_MS_FCM /* MSEL = FCM */ \ 240 | BR_V) /* valid */ 241 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 242 | OR_FCM_PGS /* Large Page*/ \ 243 | OR_FCM_CSCT \ 244 | OR_FCM_CST \ 245 | OR_FCM_CHT \ 246 | OR_FCM_SCY_1 \ 247 | OR_FCM_TRLX \ 248 | OR_FCM_EHTR) 249 250 #ifdef CONFIG_NAND 251 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 252 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 253 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 254 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 255 #else 256 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 257 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 258 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 259 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 260 #endif 261 #else 262 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 263 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 264 #endif /* CONFIG_NAND_FSL_ELBC */ 265 266 #define CONFIG_SYS_FLASH_EMPTY_INFO 267 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 268 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 269 270 #define CONFIG_MISC_INIT_R 271 272 #define CONFIG_HWCONFIG 273 274 /* define to use L1 as initial stack */ 275 #define CONFIG_L1_INIT_RAM 276 #define CONFIG_SYS_INIT_RAM_LOCK 277 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 281 /* The assembler doesn't like typecast */ 282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 283 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 284 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 285 #else 286 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 289 #endif 290 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 291 292 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 293 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 294 295 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 296 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 297 298 /* Serial Port - controlled on board with jumper J8 299 * open - index 2 300 * shorted - index 1 301 */ 302 #define CONFIG_SYS_NS16550_SERIAL 303 #define CONFIG_SYS_NS16550_REG_SIZE 1 304 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 305 306 #define CONFIG_SYS_BAUDRATE_TABLE \ 307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 308 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 311 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 312 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 313 314 /* I2C */ 315 #define CONFIG_SYS_I2C 316 #define CONFIG_SYS_I2C_FSL 317 #define CONFIG_SYS_FSL_I2C_SPEED 400000 318 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 320 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 321 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 322 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 323 324 /* 325 * RapidIO 326 */ 327 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 328 #ifdef CONFIG_PHYS_64BIT 329 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 330 #else 331 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 332 #endif 333 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 334 335 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 336 #ifdef CONFIG_PHYS_64BIT 337 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 338 #else 339 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 340 #endif 341 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 342 343 /* 344 * for slave u-boot IMAGE instored in master memory space, 345 * PHYS must be aligned based on the SIZE 346 */ 347 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 351 /* 352 * for slave UCODE and ENV instored in master memory space, 353 * PHYS must be aligned based on the SIZE 354 */ 355 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 358 359 /* slave core release by master*/ 360 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 361 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 362 363 /* 364 * SRIO_PCIE_BOOT - SLAVE 365 */ 366 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 367 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 368 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 369 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 370 #endif 371 372 /* 373 * eSPI - Enhanced SPI 374 */ 375 #define CONFIG_SF_DEFAULT_SPEED 10000000 376 #define CONFIG_SF_DEFAULT_MODE 0 377 378 /* 379 * General PCI 380 * Memory space is mapped 1-1, but I/O space must start from 0. 381 */ 382 383 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 384 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 385 #ifdef CONFIG_PHYS_64BIT 386 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 387 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 388 #else 389 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 390 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 391 #endif 392 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 393 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 394 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 395 #ifdef CONFIG_PHYS_64BIT 396 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 397 #else 398 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 399 #endif 400 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 401 402 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 403 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 404 #ifdef CONFIG_PHYS_64BIT 405 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 406 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 407 #else 408 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 409 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 410 #endif 411 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 412 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 413 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 416 #else 417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 418 #endif 419 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 420 421 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 422 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 423 #ifdef CONFIG_PHYS_64BIT 424 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 425 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 426 #else 427 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 428 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 429 #endif 430 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 431 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 432 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 435 #else 436 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 437 #endif 438 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 439 440 /* controller 4, Base address 203000 */ 441 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 442 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 443 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 444 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 445 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 446 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 447 448 /* Qman/Bman */ 449 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 450 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 451 #ifdef CONFIG_PHYS_64BIT 452 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 453 #else 454 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 455 #endif 456 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 457 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 458 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 459 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 460 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 461 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 462 CONFIG_SYS_BMAN_CENA_SIZE) 463 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 464 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 465 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 466 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 469 #else 470 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 471 #endif 472 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 473 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 474 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 475 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 476 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 477 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 478 CONFIG_SYS_QMAN_CENA_SIZE) 479 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 480 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 481 482 #define CONFIG_SYS_DPAA_FMAN 483 #define CONFIG_SYS_DPAA_PME 484 /* Default address of microcode for the Linux Fman driver */ 485 #if defined(CONFIG_SPIFLASH) 486 /* 487 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 488 * env, so we got 0x110000. 489 */ 490 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 491 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 492 #elif defined(CONFIG_SDCARD) 493 /* 494 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 495 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 496 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 497 */ 498 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 499 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 500 #elif defined(CONFIG_NAND) 501 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 502 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 503 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 504 /* 505 * Slave has no ucode locally, it can fetch this from remote. When implementing 506 * in two corenet boards, slave's ucode could be stored in master's memory 507 * space, the address can be mapped from slave TLB->slave LAW-> 508 * slave SRIO or PCIE outbound window->master inbound window-> 509 * master LAW->the ucode address in master's memory space. 510 */ 511 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 512 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 513 #else 514 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 515 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 516 #endif 517 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 518 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 519 520 #ifdef CONFIG_SYS_DPAA_FMAN 521 #define CONFIG_FMAN_ENET 522 #define CONFIG_PHYLIB_10G 523 #define CONFIG_PHY_VITESSE 524 #define CONFIG_PHY_TERANETICS 525 #endif 526 527 #ifdef CONFIG_PCI 528 #define CONFIG_PCI_INDIRECT_BRIDGE 529 530 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 531 #endif /* CONFIG_PCI */ 532 533 /* SATA */ 534 #ifdef CONFIG_FSL_SATA_V2 535 #define CONFIG_SYS_SATA_MAX_DEVICE 2 536 #define CONFIG_SATA1 537 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 538 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 539 #define CONFIG_SATA2 540 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 541 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 542 543 #define CONFIG_LBA48 544 #endif 545 546 #ifdef CONFIG_FMAN_ENET 547 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 548 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 549 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 550 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 551 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 552 553 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 554 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 555 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 556 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 557 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 558 559 #define CONFIG_SYS_TBIPA_VALUE 8 560 #define CONFIG_MII /* MII PHY management */ 561 #define CONFIG_ETHPRIME "FM1@DTSEC1" 562 #endif 563 564 /* 565 * Environment 566 */ 567 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 568 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 569 570 /* 571 * USB 572 */ 573 #define CONFIG_HAS_FSL_DR_USB 574 #define CONFIG_HAS_FSL_MPH_USB 575 576 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 577 #define CONFIG_USB_EHCI_FSL 578 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 579 #endif 580 581 #ifdef CONFIG_MMC 582 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 583 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 584 #endif 585 586 /* 587 * Miscellaneous configurable options 588 */ 589 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 590 591 /* 592 * For booting Linux, the board info and command line data 593 * have to be in the first 64 MB of memory, since this is 594 * the maximum mapped by the Linux kernel during initialization. 595 */ 596 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 597 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 598 599 #ifdef CONFIG_CMD_KGDB 600 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 601 #endif 602 603 /* 604 * Environment Configuration 605 */ 606 #define CONFIG_ROOTPATH "/opt/nfsroot" 607 #define CONFIG_BOOTFILE "uImage" 608 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 609 610 /* default location for tftp and bootm */ 611 #define CONFIG_LOADADDR 1000000 612 613 #ifdef CONFIG_TARGET_P4080DS 614 #define __USB_PHY_TYPE ulpi 615 #else 616 #define __USB_PHY_TYPE utmi 617 #endif 618 619 #define CONFIG_EXTRA_ENV_SETTINGS \ 620 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 621 "bank_intlv=cs0_cs1;" \ 622 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 623 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 624 "netdev=eth0\0" \ 625 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 626 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 627 "tftpflash=tftpboot $loadaddr $uboot && " \ 628 "protect off $ubootaddr +$filesize && " \ 629 "erase $ubootaddr +$filesize && " \ 630 "cp.b $loadaddr $ubootaddr $filesize && " \ 631 "protect on $ubootaddr +$filesize && " \ 632 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 633 "consoledev=ttyS0\0" \ 634 "ramdiskaddr=2000000\0" \ 635 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 636 "fdtaddr=1e00000\0" \ 637 "fdtfile=p4080ds/p4080ds.dtb\0" \ 638 "bdev=sda3\0" 639 640 #define CONFIG_HDBOOT \ 641 "setenv bootargs root=/dev/$bdev rw " \ 642 "console=$consoledev,$baudrate $othbootargs;" \ 643 "tftp $loadaddr $bootfile;" \ 644 "tftp $fdtaddr $fdtfile;" \ 645 "bootm $loadaddr - $fdtaddr" 646 647 #define CONFIG_NFSBOOTCOMMAND \ 648 "setenv bootargs root=/dev/nfs rw " \ 649 "nfsroot=$serverip:$rootpath " \ 650 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 651 "console=$consoledev,$baudrate $othbootargs;" \ 652 "tftp $loadaddr $bootfile;" \ 653 "tftp $fdtaddr $fdtfile;" \ 654 "bootm $loadaddr - $fdtaddr" 655 656 #define CONFIG_RAMBOOTCOMMAND \ 657 "setenv bootargs root=/dev/ram rw " \ 658 "console=$consoledev,$baudrate $othbootargs;" \ 659 "tftp $ramdiskaddr $ramdiskfile;" \ 660 "tftp $loadaddr $bootfile;" \ 661 "tftp $fdtaddr $fdtfile;" \ 662 "bootm $loadaddr $ramdiskaddr $fdtaddr" 663 664 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 665 666 #include <asm/fsl_secure_boot.h> 667 668 #endif /* __CONFIG_H */ 669