1 /* 2 * Copyright 2009-2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 /* High Level Configuration Options */ 32 #define CONFIG_BOOKE 33 #define CONFIG_E500 /* BOOKE e500 family */ 34 #define CONFIG_E500MC /* BOOKE e500mc family */ 35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 36 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 37 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 38 #define CONFIG_MP /* support multiple processors */ 39 40 #ifndef CONFIG_SYS_TEXT_BASE 41 #define CONFIG_SYS_TEXT_BASE 0xeff80000 42 #endif 43 44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 45 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 46 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 47 #define CONFIG_PCI /* Enable PCI/PCIE */ 48 #define CONFIG_PCIE1 /* PCIE controler 1 */ 49 #define CONFIG_PCIE2 /* PCIE controler 2 */ 50 #define CONFIG_PCIE3 /* PCIE controler 3 */ 51 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 52 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 53 54 #define CONFIG_SRIO1 /* SRIO port 1 */ 55 #define CONFIG_SRIO2 /* SRIO port 2 */ 56 57 #define CONFIG_FSL_LAW /* Use common FSL init code */ 58 59 #define CONFIG_ENV_OVERWRITE 60 61 #ifdef CONFIG_SYS_NO_FLASH 62 #define CONFIG_ENV_IS_NOWHERE 63 #else 64 #define CONFIG_ENV_IS_IN_FLASH 65 #define CONFIG_FLASH_CFI_DRIVER 66 #define CONFIG_SYS_FLASH_CFI 67 #endif 68 69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 70 71 /* 72 * These can be toggled for performance analysis, otherwise use default. 73 */ 74 #define CONFIG_SYS_CACHE_STASHING 75 #define CONFIG_BACKSIDE_L2_CACHE 76 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 77 #define CONFIG_BTB /* toggle branch predition */ 78 /*#define CONFIG_DDR_ECC*/ 79 #ifdef CONFIG_DDR_ECC 80 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 81 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 82 #endif 83 84 #define CONFIG_ENABLE_36BIT_PHYS 85 86 #ifdef CONFIG_PHYS_64BIT 87 #define CONFIG_ADDR_MAP 88 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 89 #endif 90 91 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 93 #define CONFIG_SYS_MEMTEST_END 0x00400000 94 #define CONFIG_SYS_ALT_MEMTEST 95 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 96 97 /* 98 * Base addresses -- Note these are effective addresses where the 99 * actual resources get mapped (not physical addresses) 100 */ 101 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ 102 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ 103 #ifdef CONFIG_PHYS_64BIT 104 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ 105 #else 106 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 107 #endif 108 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 109 110 #ifdef CONFIG_PHYS_64BIT 111 #define CONFIG_SYS_DCSRBAR 0xf0000000 112 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 113 #endif 114 115 /* EEPROM */ 116 #define CONFIG_ID_EEPROM 117 #define CONFIG_SYS_I2C_EEPROM_NXID 118 #define CONFIG_SYS_EEPROM_BUS_NUM 0 119 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 120 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 121 122 /* 123 * DDR Setup 124 */ 125 #define CONFIG_VERY_BIG_RAM 126 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 128 129 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 130 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 131 132 #define CONFIG_DDR_SPD 133 #define CONFIG_FSL_DDR3 134 135 #define CONFIG_SYS_SPD_BUS_NUM 1 136 #define SPD_EEPROM_ADDRESS1 0x51 137 #define SPD_EEPROM_ADDRESS2 0x52 138 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 139 140 /* 141 * Local Bus Definitions 142 */ 143 144 /* Set the local bus clock 1/8 of platform clock */ 145 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 146 147 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 150 #else 151 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 152 #endif 153 154 #define CONFIG_SYS_BR0_PRELIM \ 155 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 156 BR_PS_16 | BR_V) 157 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 158 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 159 160 #define CONFIG_SYS_BR1_PRELIM \ 161 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 162 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 163 164 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 165 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 166 #ifdef CONFIG_PHYS_64BIT 167 #define PIXIS_BASE_PHYS 0xfffdf0000ull 168 #else 169 #define PIXIS_BASE_PHYS PIXIS_BASE 170 #endif 171 172 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 173 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 174 175 #define PIXIS_LBMAP_SWITCH 7 176 #define PIXIS_LBMAP_MASK 0xf0 177 #define PIXIS_LBMAP_SHIFT 4 178 #define PIXIS_LBMAP_ALTBANK 0x40 179 180 #define CONFIG_SYS_FLASH_QUIET_TEST 181 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 182 183 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 184 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 185 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 186 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 187 188 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 189 190 #define CONFIG_SYS_FLASH_EMPTY_INFO 191 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 192 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 193 194 #define CONFIG_BOARD_EARLY_INIT_F 195 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 196 #define CONFIG_MISC_INIT_R 197 198 #define CONFIG_HWCONFIG 199 200 /* define to use L1 as initial stack */ 201 #define CONFIG_L1_INIT_RAM 202 #define CONFIG_SYS_INIT_RAM_LOCK 203 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 204 #ifdef CONFIG_PHYS_64BIT 205 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 206 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 207 /* The assembler doesn't like typecast */ 208 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 209 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 210 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 211 #else 212 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 213 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 214 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 215 #endif 216 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 217 218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 220 221 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 222 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 223 224 /* Serial Port - controlled on board with jumper J8 225 * open - index 2 226 * shorted - index 1 227 */ 228 #define CONFIG_CONS_INDEX 1 229 #define CONFIG_SYS_NS16550 230 #define CONFIG_SYS_NS16550_SERIAL 231 #define CONFIG_SYS_NS16550_REG_SIZE 1 232 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 233 234 #define CONFIG_SYS_BAUDRATE_TABLE \ 235 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 236 237 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 238 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 239 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 240 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 241 242 /* Use the HUSH parser */ 243 #define CONFIG_SYS_HUSH_PARSER 244 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 245 246 /* pass open firmware flat tree */ 247 #define CONFIG_OF_LIBFDT 248 #define CONFIG_OF_BOARD_SETUP 249 #define CONFIG_OF_STDOUT_VIA_ALIAS 250 251 /* new uImage format support */ 252 #define CONFIG_FIT 253 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 254 255 /* I2C */ 256 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 257 #define CONFIG_HARD_I2C /* I2C with hardware support */ 258 #define CONFIG_I2C_MULTI_BUS 259 #define CONFIG_I2C_CMD_TREE 260 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 261 #define CONFIG_SYS_I2C_SLAVE 0x7F 262 #define CONFIG_SYS_I2C_OFFSET 0x118000 263 #define CONFIG_SYS_I2C2_OFFSET 0x118100 264 265 /* 266 * RapidIO 267 */ 268 #define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 269 #ifdef CONFIG_PHYS_64BIT 270 #define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull 271 #else 272 #define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 273 #endif 274 #define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ 275 276 #define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 277 #ifdef CONFIG_PHYS_64BIT 278 #define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull 279 #else 280 #define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 281 #endif 282 #define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ 283 284 /* 285 * General PCI 286 * Memory space is mapped 1-1, but I/O space must start from 0. 287 */ 288 289 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 290 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 293 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 294 #else 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 297 #endif 298 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 299 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 300 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 301 #ifdef CONFIG_PHYS_64BIT 302 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 303 #else 304 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 305 #endif 306 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 307 308 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 309 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 310 #ifdef CONFIG_PHYS_64BIT 311 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 312 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 313 #else 314 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 315 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 316 #endif 317 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 318 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 319 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 320 #ifdef CONFIG_PHYS_64BIT 321 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 322 #else 323 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 324 #endif 325 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 326 327 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 328 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 331 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 332 #else 333 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 334 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 335 #endif 336 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 337 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 338 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 339 #ifdef CONFIG_PHYS_64BIT 340 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 341 #else 342 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 343 #endif 344 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 345 346 /* controller 4, Base address 203000 */ 347 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 348 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 349 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 350 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 351 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 352 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 353 354 /* Qman/Bman */ 355 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 356 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 359 #else 360 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 361 #endif 362 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 363 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 364 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 365 #ifdef CONFIG_PHYS_64BIT 366 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 367 #else 368 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 369 #endif 370 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 371 372 #define CONFIG_SYS_DPAA_FMAN 373 #define CONFIG_SYS_DPAA_PME 374 /* Default address of microcode for the Linux Fman driver */ 375 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 376 #ifdef CONFIG_PHYS_64BIT 377 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL 378 #else 379 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR 380 #endif 381 382 #ifdef CONFIG_SYS_DPAA_FMAN 383 #define CONFIG_FMAN_ENET 384 #endif 385 386 #ifdef CONFIG_PCI 387 388 /*PCIE video card used*/ 389 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 390 391 /* video */ 392 #define CONFIG_VIDEO 393 394 #ifdef CONFIG_VIDEO 395 #define CONFIG_BIOSEMU 396 #define CONFIG_CFB_CONSOLE 397 #define CONFIG_VIDEO_SW_CURSOR 398 #define CONFIG_VGA_AS_SINGLE_DEVICE 399 #define CONFIG_ATI_RADEON_FB 400 #define CONFIG_VIDEO_LOGO 401 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 402 #endif 403 404 #define CONFIG_NET_MULTI 405 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 406 #define CONFIG_E1000 407 408 #ifndef CONFIG_PCI_PNP 409 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 410 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 411 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 412 #endif 413 414 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 415 #define CONFIG_DOS_PARTITION 416 #endif /* CONFIG_PCI */ 417 418 /* SATA */ 419 #ifdef CONFIG_FSL_SATA_V2 420 #define CONFIG_LIBATA 421 #define CONFIG_FSL_SATA 422 423 #define CONFIG_SYS_SATA_MAX_DEVICE 2 424 #define CONFIG_SATA1 425 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 426 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 427 #define CONFIG_SATA2 428 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 429 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 430 431 #define CONFIG_LBA48 432 #define CONFIG_CMD_SATA 433 #define CONFIG_DOS_PARTITION 434 #define CONFIG_CMD_EXT2 435 #endif 436 437 #ifdef CONFIG_FMAN_ENET 438 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 439 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 440 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 441 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 442 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 443 444 #if (CONFIG_SYS_NUM_FMAN == 2) 445 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 446 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 447 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 448 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 449 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 450 #endif 451 452 #define CONFIG_SYS_TBIPA_VALUE 8 453 #define CONFIG_MII /* MII PHY management */ 454 #define CONFIG_ETHPRIME "FM1@DTSEC1" 455 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 456 #endif 457 458 /* 459 * Environment 460 */ 461 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 462 #define CONFIG_ENV_SIZE 0x2000 463 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 464 465 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 466 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 467 468 /* 469 * Command line configuration. 470 */ 471 #include <config_cmd_default.h> 472 473 #define CONFIG_CMD_ELF 474 #define CONFIG_CMD_ERRATA 475 #define CONFIG_CMD_IRQ 476 #define CONFIG_CMD_I2C 477 #define CONFIG_CMD_MII 478 #define CONFIG_CMD_PING 479 #define CONFIG_CMD_SETEXPR 480 #define CONFIG_CMD_DHCP 481 482 #ifdef CONFIG_PCI 483 #define CONFIG_CMD_PCI 484 #define CONFIG_CMD_NET 485 #endif 486 487 /* 488 * USB 489 */ 490 #define CONFIG_CMD_USB 491 #define CONFIG_USB_STORAGE 492 #define CONFIG_USB_EHCI 493 #define CONFIG_USB_EHCI_FSL 494 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 495 #define CONFIG_CMD_EXT2 496 497 #define CONFIG_MMC 498 499 #ifdef CONFIG_MMC 500 #define CONFIG_FSL_ESDHC 501 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 502 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 503 #define CONFIG_CMD_MMC 504 #define CONFIG_GENERIC_MMC 505 #define CONFIG_CMD_EXT2 506 #define CONFIG_CMD_FAT 507 #define CONFIG_DOS_PARTITION 508 #endif 509 510 /* 511 * Miscellaneous configurable options 512 */ 513 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 514 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 515 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 516 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 517 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 518 #ifdef CONFIG_CMD_KGDB 519 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 520 #else 521 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 522 #endif 523 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 524 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 525 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 526 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 527 528 /* 529 * For booting Linux, the board info and command line data 530 * have to be in the first 16 MB of memory, since this is 531 * the maximum mapped by the Linux kernel during initialization. 532 */ 533 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 534 535 #ifdef CONFIG_CMD_KGDB 536 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 537 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 538 #endif 539 540 /* 541 * Environment Configuration 542 */ 543 #define CONFIG_ROOTPATH /opt/nfsroot 544 #define CONFIG_BOOTFILE uImage 545 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 546 547 /* default location for tftp and bootm */ 548 #define CONFIG_LOADADDR 1000000 549 550 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 551 552 #define CONFIG_BAUDRATE 115200 553 554 #define CONFIG_EXTRA_ENV_SETTINGS \ 555 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 556 "bank_intlv=cs0_cs1\0" \ 557 "netdev=eth0\0" \ 558 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 559 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 560 "tftpflash=tftpboot $loadaddr $uboot && " \ 561 "protect off $ubootaddr +$filesize && " \ 562 "erase $ubootaddr +$filesize && " \ 563 "cp.b $loadaddr $ubootaddr $filesize && " \ 564 "protect on $ubootaddr +$filesize && " \ 565 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 566 "consoledev=ttyS0\0" \ 567 "ramdiskaddr=2000000\0" \ 568 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 569 "fdtaddr=c00000\0" \ 570 "fdtfile=p4080ds/p4080ds.dtb\0" \ 571 "bdev=sda3\0" \ 572 "c=ffe\0" \ 573 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" 574 575 #define CONFIG_HDBOOT \ 576 "setenv bootargs root=/dev/$bdev rw " \ 577 "console=$consoledev,$baudrate $othbootargs;" \ 578 "tftp $loadaddr $bootfile;" \ 579 "tftp $fdtaddr $fdtfile;" \ 580 "bootm $loadaddr - $fdtaddr" 581 582 #define CONFIG_NFSBOOTCOMMAND \ 583 "setenv bootargs root=/dev/nfs rw " \ 584 "nfsroot=$serverip:$rootpath " \ 585 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 586 "console=$consoledev,$baudrate $othbootargs;" \ 587 "tftp $loadaddr $bootfile;" \ 588 "tftp $fdtaddr $fdtfile;" \ 589 "bootm $loadaddr - $fdtaddr" 590 591 #define CONFIG_RAMBOOTCOMMAND \ 592 "setenv bootargs root=/dev/ram rw " \ 593 "console=$consoledev,$baudrate $othbootargs;" \ 594 "tftp $ramdiskaddr $ramdiskfile;" \ 595 "tftp $loadaddr $bootfile;" \ 596 "tftp $fdtaddr $fdtfile;" \ 597 "bootm $loadaddr $ramdiskaddr $fdtaddr" 598 599 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 600 601 #endif /* __CONFIG_H */ 602