1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 28883ddafSNikita Kiryanov /* 38883ddafSNikita Kiryanov * cm_t43.h 48883ddafSNikita Kiryanov * 58883ddafSNikita Kiryanov * Copyright (C) 2015 Compulab, Ltd. 68883ddafSNikita Kiryanov */ 78883ddafSNikita Kiryanov 88883ddafSNikita Kiryanov #ifndef __CONFIG_CM_T43_H 98883ddafSNikita Kiryanov #define __CONFIG_CM_T43_H 108883ddafSNikita Kiryanov 118883ddafSNikita Kiryanov #define CONFIG_CM_T43 128883ddafSNikita Kiryanov #define CONFIG_ARCH_CPU_INIT 138883ddafSNikita Kiryanov #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ 148883ddafSNikita Kiryanov #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 158883ddafSNikita Kiryanov 168883ddafSNikita Kiryanov #include <asm/arch/omap.h> 178883ddafSNikita Kiryanov 188883ddafSNikita Kiryanov /* Serial support */ 198883ddafSNikita Kiryanov #define CONFIG_SYS_NS16550_SERIAL 208883ddafSNikita Kiryanov #define CONFIG_SYS_NS16550_CLK 48000000 218883ddafSNikita Kiryanov #define CONFIG_SYS_NS16550_COM1 0x44e09000 22f2d78c1cSTom Rini #if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) 237ef77c02SNikita Kiryanov #define CONFIG_SYS_NS16550_REG_SIZE (-4) 247ef77c02SNikita Kiryanov #endif 258883ddafSNikita Kiryanov 268883ddafSNikita Kiryanov /* NAND support */ 278883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_ONFI_DETECTION 288883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_5_ADDR_CYCLE 298883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_PAGE_SIZE 2048 308883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_OOBSIZE 64 318883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 328883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 338883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_ECCSIZE 512 348883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_ECCBYTES 14 358883ddafSNikita Kiryanov #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 368883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 378883ddafSNikita Kiryanov CONFIG_SYS_NAND_PAGE_SIZE) 388883ddafSNikita Kiryanov #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 398883ddafSNikita Kiryanov 10, 11, 12, 13, 14, 15, 16, 17, \ 408883ddafSNikita Kiryanov 18, 19, 20, 21, 22, 23, 24, 25, \ 418883ddafSNikita Kiryanov 26, 27, 28, 29, 30, 31, 32, 33, \ 428883ddafSNikita Kiryanov 34, 35, 36, 37, 38, 39, 40, 41, \ 438883ddafSNikita Kiryanov 42, 43, 44, 45, 46, 47, 48, 49, \ 448883ddafSNikita Kiryanov 50, 51, 52, 53, 54, 55, 56, 57, } 458883ddafSNikita Kiryanov 468883ddafSNikita Kiryanov /* CPSW Ethernet support */ 478883ddafSNikita Kiryanov #define CONFIG_BOOTP_DEFAULT 488883ddafSNikita Kiryanov #define CONFIG_BOOTP_SEND_HOSTNAME 498883ddafSNikita Kiryanov #define CONFIG_PHY_ATHEROS 508883ddafSNikita Kiryanov #define CONFIG_SYS_RX_ETH_BUFFER 64 518883ddafSNikita Kiryanov 528883ddafSNikita Kiryanov /* USB support */ 538883ddafSNikita Kiryanov #define CONFIG_USB_XHCI_OMAP 548883ddafSNikita Kiryanov #define CONFIG_AM437X_USB2PHY2_HOST 558883ddafSNikita Kiryanov 568883ddafSNikita Kiryanov /* SPI Flash support */ 578883ddafSNikita Kiryanov #define CONFIG_TI_SPI_MMAP 588883ddafSNikita Kiryanov 598883ddafSNikita Kiryanov /* Power */ 608883ddafSNikita Kiryanov #define CONFIG_POWER 618883ddafSNikita Kiryanov #define CONFIG_POWER_I2C 628883ddafSNikita Kiryanov #define CONFIG_POWER_TPS65218 638883ddafSNikita Kiryanov 648883ddafSNikita Kiryanov /* Enabling L2 Cache */ 658883ddafSNikita Kiryanov #define CONFIG_SYS_L2_PL310 668883ddafSNikita Kiryanov #define CONFIG_SYS_PL310_BASE 0x48242000 678883ddafSNikita Kiryanov 688883ddafSNikita Kiryanov /* 698883ddafSNikita Kiryanov * Since SPL did pll and ddr initialization for us, 708883ddafSNikita Kiryanov * we don't need to do it twice. 718883ddafSNikita Kiryanov */ 728883ddafSNikita Kiryanov #if !defined(CONFIG_SPL_BUILD) 738883ddafSNikita Kiryanov #define CONFIG_SKIP_LOWLEVEL_INIT 748883ddafSNikita Kiryanov #endif 758883ddafSNikita Kiryanov 768883ddafSNikita Kiryanov #define CONFIG_HSMMC2_8BIT 778883ddafSNikita Kiryanov 788883ddafSNikita Kiryanov #include <configs/ti_armv7_omap.h> 797d751d66SNikita Kiryanov #undef CONFIG_SYS_MONITOR_LEN 808883ddafSNikita Kiryanov 818883ddafSNikita Kiryanov #define CONFIG_ENV_SIZE (16 * 1024) 828883ddafSNikita Kiryanov 838883ddafSNikita Kiryanov #define V_OSCK 24000000 /* Clock output from T2 */ 848883ddafSNikita Kiryanov #define V_SCLK (V_OSCK) 858883ddafSNikita Kiryanov 868883ddafSNikita Kiryanov #define CONFIG_ENV_SECT_SIZE (64 * 1024) 878883ddafSNikita Kiryanov #define CONFIG_ENV_OFFSET (768 * 1024) 888883ddafSNikita Kiryanov 898883ddafSNikita Kiryanov #define CONFIG_EXTRA_ENV_SETTINGS \ 908883ddafSNikita Kiryanov "loadaddr=0x80200000\0" \ 918883ddafSNikita Kiryanov "fdtaddr=0x81200000\0" \ 928883ddafSNikita Kiryanov "bootm_size=0x8000000\0" \ 938883ddafSNikita Kiryanov "autoload=no\0" \ 948883ddafSNikita Kiryanov "console=ttyO0,115200n8\0" \ 958883ddafSNikita Kiryanov "fdtfile=am437x-sb-som-t43.dtb\0" \ 968883ddafSNikita Kiryanov "kernel=zImage-cm-t43\0" \ 978883ddafSNikita Kiryanov "bootscr=bootscr.img\0" \ 988883ddafSNikita Kiryanov "emmcroot=/dev/mmcblk0p2 rw\0" \ 998883ddafSNikita Kiryanov "emmcrootfstype=ext4 rootwait\0" \ 1008883ddafSNikita Kiryanov "emmcargs=setenv bootargs console=${console} " \ 1018883ddafSNikita Kiryanov "root=${emmcroot} " \ 1028883ddafSNikita Kiryanov "rootfstype=${emmcrootfstype}\0" \ 1038883ddafSNikita Kiryanov "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ 1048883ddafSNikita Kiryanov "bootscript=echo Running bootscript from mmc ...; " \ 1058883ddafSNikita Kiryanov "source ${loadaddr}\0" \ 1068883ddafSNikita Kiryanov "emmcboot=echo Booting from emmc ... && " \ 1078883ddafSNikita Kiryanov "run emmcargs && " \ 1088883ddafSNikita Kiryanov "load mmc 1 ${loadaddr} ${kernel} && " \ 1098883ddafSNikita Kiryanov "load mmc 1 ${fdtaddr} ${fdtfile} && " \ 1108883ddafSNikita Kiryanov "bootz ${loadaddr} - ${fdtaddr}\0" 1118883ddafSNikita Kiryanov 1128883ddafSNikita Kiryanov #define CONFIG_BOOTCOMMAND \ 1138883ddafSNikita Kiryanov "mmc dev 0; " \ 1148883ddafSNikita Kiryanov "if mmc rescan; then " \ 1158883ddafSNikita Kiryanov "if run loadbootscript; then " \ 1168883ddafSNikita Kiryanov "run bootscript; " \ 1178883ddafSNikita Kiryanov "fi; " \ 1188883ddafSNikita Kiryanov "fi; " \ 1198883ddafSNikita Kiryanov "mmc dev 1; " \ 1208883ddafSNikita Kiryanov "if mmc rescan; then " \ 1218883ddafSNikita Kiryanov "run emmcboot; " \ 1228883ddafSNikita Kiryanov "fi;" 1238883ddafSNikita Kiryanov 1248883ddafSNikita Kiryanov /* SPL defines. */ 1258883ddafSNikita Kiryanov #define CONFIG_SPL_TEXT_BASE 0x40300350 1268883ddafSNikita Kiryanov #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) 1278883ddafSNikita Kiryanov #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) 1287d751d66SNikita Kiryanov #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 1298883ddafSNikita Kiryanov 1302d9a76b6SNikita Kiryanov /* EEPROM */ 1312d9a76b6SNikita Kiryanov #define CONFIG_ENV_EEPROM_IS_ON_I2C 1322d9a76b6SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 1332d9a76b6SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 1342d9a76b6SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 1352d9a76b6SNikita Kiryanov #define CONFIG_SYS_EEPROM_SIZE 256 1362d9a76b6SNikita Kiryanov 1378883ddafSNikita Kiryanov #endif /* __CONFIG_CM_T43_H */ 138