1*25c7de22SPaul Burton /* SPDX-License-Identifier: GPL-2.0+ */ 2*25c7de22SPaul Burton /* 3*25c7de22SPaul Burton * CI20 configuration 4*25c7de22SPaul Burton * 5*25c7de22SPaul Burton * Copyright (c) 2013 Imagination Technologies 6*25c7de22SPaul Burton * Author: Paul Burton <paul.burton@imgtec.com> 7*25c7de22SPaul Burton */ 8*25c7de22SPaul Burton 9*25c7de22SPaul Burton #ifndef __CONFIG_CI20_H__ 10*25c7de22SPaul Burton #define __CONFIG_CI20_H__ 11*25c7de22SPaul Burton 12*25c7de22SPaul Burton #define CONFIG_SKIP_LOWLEVEL_INIT 13*25c7de22SPaul Burton 14*25c7de22SPaul Burton /* Ingenic JZ4780 clock configuration. */ 15*25c7de22SPaul Burton #define CONFIG_SYS_HZ 1000 16*25c7de22SPaul Burton #define CONFIG_SYS_MHZ 1200 17*25c7de22SPaul Burton #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 18*25c7de22SPaul Burton 19*25c7de22SPaul Burton /* Memory configuration */ 20*25c7de22SPaul Burton #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 21*25c7de22SPaul Burton #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 22*25c7de22SPaul Burton #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) 23*25c7de22SPaul Burton 24*25c7de22SPaul Burton #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ 25*25c7de22SPaul Burton #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 26*25c7de22SPaul Burton #define CONFIG_SYS_LOAD_ADDR 0x81000000 27*25c7de22SPaul Burton #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 28*25c7de22SPaul Burton #define CONFIG_SYS_MEMTEST_START 0x80000000 29*25c7de22SPaul Burton #define CONFIG_SYS_MEMTEST_END 0x88000000 30*25c7de22SPaul Burton 31*25c7de22SPaul Burton #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 32*25c7de22SPaul Burton 33*25c7de22SPaul Burton /* NS16550-ish UARTs */ 34*25c7de22SPaul Burton #define CONFIG_SYS_NS16550_CLK 48000000 35*25c7de22SPaul Burton #define CONFIG_SYS_CONSOLE_IS_IN_ENV 36*25c7de22SPaul Burton 37*25c7de22SPaul Burton /* Ethernet: davicom DM9000 */ 38*25c7de22SPaul Burton #define CONFIG_DRIVER_DM9000 1 39*25c7de22SPaul Burton #define CONFIG_DM9000_BASE 0xb6000000 40*25c7de22SPaul Burton #define DM9000_IO CONFIG_DM9000_BASE 41*25c7de22SPaul Burton #define DM9000_DATA (CONFIG_DM9000_BASE + 2) 42*25c7de22SPaul Burton 43*25c7de22SPaul Burton /* Environment */ 44*25c7de22SPaul Burton #define CONFIG_SYS_MMC_ENV_DEV 0 45*25c7de22SPaul Burton #define CONFIG_ENV_SIZE (32 << 10) 46*25c7de22SPaul Burton #define CONFIG_ENV_OFFSET ((14 + 512) << 10) 47*25c7de22SPaul Burton #define CONFIG_ENV_OVERWRITE 48*25c7de22SPaul Burton 49*25c7de22SPaul Burton /* Command line configuration. */ 50*25c7de22SPaul Burton #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 51*25c7de22SPaul Burton #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 52*25c7de22SPaul Burton #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 53*25c7de22SPaul Burton /* Boot argument buffer size */ 54*25c7de22SPaul Burton #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 55*25c7de22SPaul Burton 56*25c7de22SPaul Burton /* Miscellaneous configuration options */ 57*25c7de22SPaul Burton #define CONFIG_SYS_BOOTM_LEN (64 << 20) 58*25c7de22SPaul Burton 59*25c7de22SPaul Burton /* SPL */ 60*25c7de22SPaul Burton #define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ 61*25c7de22SPaul Burton 62*25c7de22SPaul Burton #define CONFIG_SPL_TEXT_BASE 0xf4000a00 63*25c7de22SPaul Burton #define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) 64*25c7de22SPaul Burton 65*25c7de22SPaul Burton #define CONFIG_SPL_BSS_START_ADDR 0xf4004000 66*25c7de22SPaul Burton #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ 67*25c7de22SPaul Burton 68*25c7de22SPaul Burton #define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" 69*25c7de22SPaul Burton 70*25c7de22SPaul Burton #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */ 71*25c7de22SPaul Burton 72*25c7de22SPaul Burton #endif /* __CONFIG_CI20_H__ */ 73