1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 /* 45 * Hardware drivers 46 */ 47 #define CONFIG_ATMEL_LEGACY 48 49 /* LCD */ 50 #define LCD_BPP LCD_COLOR8 51 #define CONFIG_LCD_LOGO 1 52 #undef LCD_TEST_PATTERN 53 #define CONFIG_LCD_INFO 1 54 #define CONFIG_LCD_INFO_BELOW_LOGO 1 55 #define CONFIG_ATMEL_LCD 1 56 #define CONFIG_ATMEL_LCD_BGR555 1 57 58 /* 59 * BOOTP options 60 */ 61 #define CONFIG_BOOTP_BOOTFILESIZE 1 62 #define CONFIG_BOOTP_BOOTPATH 1 63 #define CONFIG_BOOTP_GATEWAY 1 64 #define CONFIG_BOOTP_HOSTNAME 1 65 66 /* SDRAM */ 67 #define CONFIG_NR_DRAM_BANKS 1 68 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 69 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 70 71 #define CONFIG_SYS_INIT_SP_ADDR \ 72 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 73 74 /* DataFlash */ 75 #define CONFIG_ATMEL_DATAFLASH_SPI 76 #define CONFIG_HAS_DATAFLASH 1 77 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 78 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 79 #define AT91_SPI_CLK 15000000 80 #define DATAFLASH_TCSS (0x1a << 16) 81 #define DATAFLASH_TCHS (0x1 << 24) 82 83 /* NOR flash, if populated */ 84 #ifdef CONFIG_SYS_USE_NORFLASH 85 #define CONFIG_SYS_FLASH_CFI 1 86 #define CONFIG_FLASH_CFI_DRIVER 1 87 #define PHYS_FLASH_1 0x10000000 88 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 89 #define CONFIG_SYS_MAX_FLASH_SECT 256 90 #define CONFIG_SYS_MAX_FLASH_BANKS 1 91 92 #define CONFIG_SYS_MONITOR_SEC 1:0-3 93 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 94 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 95 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 96 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 97 98 /* Address and size of Primary Environment Sector */ 99 #define CONFIG_ENV_SIZE 0x10000 100 101 #define CONFIG_EXTRA_ENV_SETTINGS \ 102 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 103 "update=" \ 104 "protect off ${monitor_base} +${filesize};" \ 105 "erase ${monitor_base} +${filesize};" \ 106 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 107 "protect on ${monitor_base} +${filesize}\0" 108 109 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 110 #define MASTER_PLL_MUL 171 111 #define MASTER_PLL_DIV 14 112 #define MASTER_PLL_OUT 3 113 114 /* clocks */ 115 #define CONFIG_SYS_MOR_VAL \ 116 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 117 #define CONFIG_SYS_PLLAR_VAL \ 118 (AT91_PMC_PLLAR_29 | \ 119 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 120 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 121 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 122 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 123 124 /* PCK/2 = MCK Master Clock from PLLA */ 125 #define CONFIG_SYS_MCKR1_VAL \ 126 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 127 AT91_PMC_MCKR_MDIV_2) 128 129 /* PCK/2 = MCK Master Clock from PLLA */ 130 #define CONFIG_SYS_MCKR2_VAL \ 131 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 132 AT91_PMC_MCKR_MDIV_2) 133 134 /* define PDC[31:16] as DATA[31:16] */ 135 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 136 /* no pull-up for D[31:16] */ 137 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 138 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 139 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 140 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 141 AT91_MATRIX_CSA_EBI_CS1A) 142 143 /* SDRAM */ 144 /* SDRAMC_MR Mode register */ 145 #define CONFIG_SYS_SDRC_MR_VAL1 0 146 /* SDRAMC_TR - Refresh Timer register */ 147 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 148 /* SDRAMC_CR - Configuration register*/ 149 #define CONFIG_SYS_SDRC_CR_VAL \ 150 (AT91_SDRAMC_NC_9 | \ 151 AT91_SDRAMC_NR_13 | \ 152 AT91_SDRAMC_NB_4 | \ 153 AT91_SDRAMC_CAS_3 | \ 154 AT91_SDRAMC_DBW_32 | \ 155 (1 << 8) | /* Write Recovery Delay */ \ 156 (7 << 12) | /* Row Cycle Delay */ \ 157 (2 << 16) | /* Row Precharge Delay */ \ 158 (2 << 20) | /* Row to Column Delay */ \ 159 (5 << 24) | /* Active to Precharge Delay */ \ 160 (1 << 28)) /* Exit Self Refresh to Active Delay */ 161 162 /* Memory Device Register -> SDRAM */ 163 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 164 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 165 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 166 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 167 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 168 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 169 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 170 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 171 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 172 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 173 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 174 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 175 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 176 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 177 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 178 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 179 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 180 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 181 182 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 183 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 184 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 185 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 186 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 187 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 188 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 189 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 190 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 191 #define CONFIG_SYS_SMC0_MODE0_VAL \ 192 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 193 AT91_SMC_MODE_DBW_16 | \ 194 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 195 196 /* user reset enable */ 197 #define CONFIG_SYS_RSTC_RMR_VAL \ 198 (AT91_RSTC_KEY | \ 199 AT91_RSTC_MR_URSTEN | \ 200 AT91_RSTC_MR_ERSTL(15)) 201 202 /* Disable Watchdog */ 203 #define CONFIG_SYS_WDTC_WDMR_VAL \ 204 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 205 AT91_WDT_MR_WDV(0xfff) | \ 206 AT91_WDT_MR_WDDIS | \ 207 AT91_WDT_MR_WDD(0xfff)) 208 209 #endif 210 #endif 211 212 /* NAND flash */ 213 #ifdef CONFIG_CMD_NAND 214 #define CONFIG_NAND_ATMEL 215 #define CONFIG_SYS_MAX_NAND_DEVICE 1 216 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 217 #define CONFIG_SYS_NAND_DBW_8 1 218 /* our ALE is AD21 */ 219 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 220 /* our CLE is AD22 */ 221 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 222 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 223 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 224 #endif 225 226 /* Ethernet */ 227 #define CONFIG_RESET_PHY_R 1 228 #define CONFIG_AT91_WANTS_COMMON_PHY 229 230 /* USB */ 231 #define CONFIG_USB_ATMEL 232 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 233 #define CONFIG_USB_OHCI_NEW 1 234 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 235 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 236 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 237 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 238 239 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 240 241 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 242 #define CONFIG_SYS_MEMTEST_END 0x23e00000 243 244 #ifdef CONFIG_SYS_USE_DATAFLASH 245 246 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 247 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 248 #define CONFIG_ENV_OFFSET 0x4200 249 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 250 #define CONFIG_ENV_SIZE 0x4200 251 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 252 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 253 "root=/dev/mtdblock0 " \ 254 "mtdparts=atmel_nand:-(root) "\ 255 "rw rootfstype=jffs2" 256 257 #elif CONFIG_SYS_USE_NANDFLASH 258 259 /* bootstrap + u-boot + env + linux in nandflash */ 260 #define CONFIG_ENV_OFFSET 0x120000 261 #define CONFIG_ENV_OFFSET_REDUND 0x100000 262 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 263 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 264 #define CONFIG_BOOTARGS \ 265 "console=ttyS0,115200 earlyprintk " \ 266 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 267 "256k(env),256k(env_redundant),256k(spare)," \ 268 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 269 "root=/dev/mtdblock7 rw rootfstype=jffs2" 270 #endif 271 272 #define CONFIG_SYS_CBSIZE 256 273 #define CONFIG_SYS_MAXARGS 16 274 #define CONFIG_SYS_LONGHELP 1 275 #define CONFIG_CMDLINE_EDITING 1 276 #define CONFIG_AUTO_COMPLETE 277 278 /* 279 * Size of malloc() pool 280 */ 281 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 282 283 #endif 284