1 /* 2 * Sysam AMCORE board configuration 3 * 4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __AMCORE_CONFIG_H 10 #define __AMCORE_CONFIG_H 11 12 #define CONFIG_AMCORE 13 #define CONFIG_HOSTNAME AMCORE 14 15 #define CONFIG_SYS_GENERIC_BOARD 16 17 #define CONFIG_MCF530x 18 #define CONFIG_M5307 19 20 #define CONFIG_MCFTMR 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT 0 23 #define CONFIG_BAUDRATE 115200 24 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 25 26 #define CONFIG_BOOTDELAY 1 27 #define CONFIG_BOOTCOMMAND "bootm ffc20000" 28 29 #include <config_cmd_default.h> 30 #undef CONFIG_CMD_AES 31 #undef CONFIG_CMD_BOOTD 32 #undef CONFIG_CMD_NET 33 #undef CONFIG_CMD_NFS 34 #undef CONFIG_CMD_FPGA 35 #undef CONFIG_CMD_XIMG 36 #define CONFIG_CMD_CACHE 37 #define CONFIG_CMD_TIMER 38 #define CONFIG_CMD_DIAG 39 40 #define CONFIG_SYS_PROMPT "amcore $ " 41 /* undef to save memory */ 42 #undef CONFIG_SYS_LONGHELP 43 44 #if defined(CONFIG_CMD_KGDB) 45 /* Console I/O buff. size */ 46 #define CONFIG_SYS_CBSIZE 1024 47 #else 48 #define CONFIG_SYS_CBSIZE 256 49 #endif 50 /* Print buffer size */ 51 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 52 sizeof(CONFIG_SYS_PROMPT)+16) 53 /* max number of command args */ 54 #define CONFIG_SYS_MAXARGS 16 55 /* Boot argument buffer size */ 56 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 57 58 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */ 59 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 60 #define CONFIG_LOOPW 1 /* enable loopw command */ 61 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 62 63 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ 64 65 #define CONFIG_SYS_MEMTEST_START 0x0 66 #define CONFIG_SYS_MEMTEST_END 0x1000000 67 68 #define CONFIG_SYS_HZ 1000 69 70 #define CONFIG_SYS_CLK 45000000 71 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) 72 /* Register Base Addrs */ 73 #define CONFIG_SYS_MBAR 0x10000000 74 /* Definitions for initial stack pointer and data area (in DPRAM) */ 75 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 76 /* size of internal SRAM */ 77 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 78 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 79 GENERATED_GBL_DATA_SIZE) 80 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 81 82 #define CONFIG_SYS_SDRAM_BASE 0x00000000 83 #define CONFIG_SYS_SDRAM_SIZE 0x1000000 84 #define CONFIG_SYS_FLASH_BASE 0xffc00000 85 #define CONFIG_SYS_MAX_FLASH_BANKS 1 86 #define CONFIG_SYS_MAX_FLASH_SECT 1024 87 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 88 89 #define CONFIG_SYS_FLASH_CFI 90 #define CONFIG_FLASH_CFI_DRIVER 91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 92 /* amcore design has flash data bytes wired swapped */ 93 #define CONFIG_SYS_WRITE_SWAPPED_DATA 94 /* reserve 128-4KB */ 95 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 96 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) 97 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 98 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 99 100 #define CONFIG_ENV_IS_IN_FLASH 1 101 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 102 CONFIG_SYS_MONITOR_LEN) 103 #define CONFIG_ENV_SIZE 0x1000 104 #define CONFIG_ENV_SECT_SIZE 0x1000 105 106 /* memory map space for linux boot data */ 107 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 108 109 /* 110 * Cache Configuration 111 * 112 * Special 8K version 3 core cache. 113 * This is a single unified instruction/data cache. 114 * sdram - single region - no masks 115 */ 116 #define CONFIG_SYS_CACHELINE_SIZE 16 117 118 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 119 CONFIG_SYS_INIT_RAM_SIZE - 8) 120 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 121 CONFIG_SYS_INIT_RAM_SIZE - 4) 122 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 123 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ 124 CF_ACR_EN) 125 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ 126 CF_CACR_EC) 127 128 /* CS0 - AMD Flash, address 0xffc00000 */ 129 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) 130 /* 4MB, AA=0,V=1 C/I BIT for errata */ 131 #define CONFIG_SYS_CS0_MASK 0x003f0001 132 /* WS=10, AA=1, PS=16bit (10) */ 133 #define CONFIG_SYS_CS0_CTRL 0x1980 134 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ 135 #define CONFIG_SYS_CS1_BASE 0x3000 136 #define CONFIG_SYS_CS1_MASK 0x00070001 137 #define CONFIG_SYS_CS1_CTRL 0x0100 138 139 #endif /* __AMCORE_CONFIG_H */ 140 141