1 /* 2 * am3517_evm.h - Default configuration for AM3517 EVM board. 3 * 4 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5 * 6 * Based on omap3_evm_config.h 7 * 8 * Copyright (C) 2010 Texas Instruments Incorporated 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 20 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ 21 #define CONFIG_OMAP_COMMON 22 /* Common ARM Erratas */ 23 #define CONFIG_ARM_ERRATA_454179 24 #define CONFIG_ARM_ERRATA_430973 25 #define CONFIG_ARM_ERRATA_621766 26 27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 28 29 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/omap.h> 31 32 /* 33 * Display CPU and Board information 34 */ 35 #define CONFIG_DISPLAY_CPUINFO 1 36 #define CONFIG_DISPLAY_BOARDINFO 1 37 38 /* Clock Defines */ 39 #define V_OSCK 26000000 /* Clock output from T2 */ 40 #define V_SCLK (V_OSCK >> 1) 41 42 #define CONFIG_MISC_INIT_R 43 44 #define CONFIG_OF_LIBFDT 45 46 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 47 #define CONFIG_SETUP_MEMORY_TAGS 1 48 #define CONFIG_INITRD_TAG 1 49 #define CONFIG_REVISION_TAG 1 50 51 /* 52 * Size of malloc() pool 53 */ 54 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 56 /* 57 * DDR related 58 */ 59 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 60 61 /* 62 * Hardware drivers 63 */ 64 65 /* 66 * OMAP GPIO configuration 67 */ 68 #define CONFIG_OMAP_GPIO 69 70 /* 71 * NS16550 Configuration 72 */ 73 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 74 75 #define CONFIG_SYS_NS16550 76 #define CONFIG_SYS_NS16550_SERIAL 77 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 78 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 79 80 /* 81 * select serial console configuration 82 */ 83 #define CONFIG_CONS_INDEX 3 84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 85 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 86 87 /* allow to overwrite serial and ethaddr */ 88 #define CONFIG_ENV_OVERWRITE 89 #define CONFIG_BAUDRATE 115200 90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 91 115200} 92 #define CONFIG_MMC 1 93 #define CONFIG_GENERIC_MMC 1 94 #define CONFIG_OMAP_HSMMC 1 95 #define CONFIG_DOS_PARTITION 1 96 97 /* 98 * USB configuration 99 * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard 100 * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. 101 */ 102 #define CONFIG_USB_MUSB_AM35X 103 #define CONFIG_USB_MUSB_HOST 104 #define CONFIG_USB_MUSB_PIO_ONLY 105 106 #ifdef CONFIG_USB_MUSB_AM35X 107 108 #ifdef CONFIG_USB_MUSB_HOST 109 #define CONFIG_CMD_USB 110 111 #define CONFIG_USB_STORAGE 112 #define CONGIG_CMD_STORAGE 113 #define CONFIG_CMD_FAT 114 115 #ifdef CONFIG_USB_KEYBOARD 116 #define CONFIG_SYS_USB_EVENT_POLL 117 #define CONFIG_PREBOOT "usb start" 118 #endif /* CONFIG_USB_KEYBOARD */ 119 120 #endif /* CONFIG_USB_MUSB_HOST */ 121 122 #ifdef CONFIG_USB_MUSB_GADGET 123 #define CONFIG_USB_GADGET_DUALSPEED 124 #define CONFIG_USB_ETHER 125 #define CONFIG_USB_ETH_RNDIS 126 #endif /* CONFIG_USB_MUSB_GADGET */ 127 128 #endif /* CONFIG_USB_MUSB_AM35X */ 129 130 /* commands to include */ 131 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 132 #define CONFIG_CMD_FAT /* FAT support */ 133 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 134 135 #define CONFIG_CMD_I2C /* I2C serial bus support */ 136 #define CONFIG_CMD_MMC /* MMC support */ 137 #define CONFIG_CMD_NAND /* NAND support */ 138 #define CONFIG_CMD_DHCP 139 #undef CONFIG_CMD_PING 140 141 142 #define CONFIG_SYS_NO_FLASH 143 #define CONFIG_SYS_I2C 144 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 145 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 146 #define CONFIG_SYS_I2C_OMAP34XX 147 148 /* 149 * Ethernet 150 */ 151 #define CONFIG_DRIVER_TI_EMAC 152 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 153 #define CONFIG_MII 154 #define CONFIG_BOOTP_DEFAULT 155 #define CONFIG_BOOTP_DNS 156 #define CONFIG_BOOTP_DNS2 157 #define CONFIG_BOOTP_SEND_HOSTNAME 158 #define CONFIG_NET_RETRY_COUNT 10 159 160 /* 161 * Board NAND Info. 162 */ 163 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 164 /* to access nand */ 165 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 166 /* to access */ 167 /* nand at CS0 */ 168 169 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 170 /* NAND devices */ 171 #define CONFIG_JFFS2_NAND 172 /* nand device jffs2 lives on */ 173 #define CONFIG_JFFS2_DEV "nand0" 174 /* start of jffs2 partition */ 175 #define CONFIG_JFFS2_PART_OFFSET 0x680000 176 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 177 178 /* Environment information */ 179 #define CONFIG_BOOTDELAY 10 180 181 #define CONFIG_BOOTFILE "uImage" 182 183 #define CONFIG_EXTRA_ENV_SETTINGS \ 184 "loadaddr=0x82000000\0" \ 185 "console=ttyO2,115200n8\0" \ 186 "mmcdev=0\0" \ 187 "mmcargs=setenv bootargs console=${console} " \ 188 "root=/dev/mmcblk0p2 rw rootwait\0" \ 189 "nandargs=setenv bootargs console=${console} " \ 190 "root=/dev/mtdblock4 rw " \ 191 "rootfstype=jffs2\0" \ 192 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 193 "bootscript=echo Running bootscript from mmc ...; " \ 194 "source ${loadaddr}\0" \ 195 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 196 "mmcboot=echo Booting from mmc ...; " \ 197 "run mmcargs; " \ 198 "bootm ${loadaddr}\0" \ 199 "nandboot=echo Booting from nand ...; " \ 200 "run nandargs; " \ 201 "nand read ${loadaddr} 280000 400000; " \ 202 "bootm ${loadaddr}\0" \ 203 204 #define CONFIG_BOOTCOMMAND \ 205 "mmc dev ${mmcdev}; if mmc rescan; then " \ 206 "if run loadbootscript; then " \ 207 "run bootscript; " \ 208 "else " \ 209 "if run loaduimage; then " \ 210 "run mmcboot; " \ 211 "else run nandboot; " \ 212 "fi; " \ 213 "fi; " \ 214 "else run nandboot; fi" 215 216 #define CONFIG_AUTO_COMPLETE 1 217 /* 218 * Miscellaneous configurable options 219 */ 220 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 221 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 222 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 223 /* Print Buffer Size */ 224 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 225 sizeof(CONFIG_SYS_PROMPT) + 16) 226 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 227 /* args */ 228 /* Boot Argument Buffer Size */ 229 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 230 /* memtest works on */ 231 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 232 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 233 0x01F00000) /* 31MB */ 234 235 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 236 /* address */ 237 238 /* 239 * AM3517 has 12 GP timers, they can be driven by the system clock 240 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 241 * This rate is divided by a local divisor. 242 */ 243 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 244 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 245 246 /*----------------------------------------------------------------------- 247 * Physical Memory Map 248 */ 249 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 250 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 251 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 252 253 /*----------------------------------------------------------------------- 254 * FLASH and environment organization 255 */ 256 257 /* **** PISMO SUPPORT *** */ 258 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 259 /* on one chip */ 260 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 261 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 262 263 #if defined(CONFIG_CMD_NAND) 264 #define CONFIG_SYS_FLASH_BASE NAND_BASE 265 #endif 266 267 /* Monitor at start of flash */ 268 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 269 270 #define CONFIG_NAND_OMAP_GPMC 271 #define CONFIG_ENV_IS_IN_NAND 1 272 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 273 274 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 275 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 276 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 277 278 /*----------------------------------------------------------------------- 279 * CFI FLASH driver setup 280 */ 281 /* timeout values are in ticks */ 282 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 283 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 284 285 /* Flash banks JFFS2 should use */ 286 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 287 CONFIG_SYS_MAX_NAND_DEVICE) 288 #define CONFIG_SYS_JFFS2_MEM_NAND 289 /* use flash_info[2] */ 290 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 291 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 292 293 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 294 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 295 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 296 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 297 CONFIG_SYS_INIT_RAM_SIZE - \ 298 GENERATED_GBL_DATA_SIZE) 299 300 /* Defines for SPL */ 301 #define CONFIG_SPL_FRAMEWORK 302 #define CONFIG_SPL_BOARD_INIT 303 #define CONFIG_SPL_NAND_SIMPLE 304 #define CONFIG_SPL_TEXT_BASE 0x40200800 305 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 306 307 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 308 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 309 310 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 311 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 312 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 313 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 314 315 #define CONFIG_SPL_LIBCOMMON_SUPPORT 316 #define CONFIG_SPL_LIBDISK_SUPPORT 317 #define CONFIG_SPL_I2C_SUPPORT 318 #define CONFIG_SPL_LIBGENERIC_SUPPORT 319 #define CONFIG_SPL_MMC_SUPPORT 320 #define CONFIG_SPL_FAT_SUPPORT 321 #define CONFIG_SPL_SERIAL_SUPPORT 322 #define CONFIG_SPL_NAND_SUPPORT 323 #define CONFIG_SPL_NAND_BASE 324 #define CONFIG_SPL_NAND_DRIVERS 325 #define CONFIG_SPL_NAND_ECC 326 #define CONFIG_SPL_POWER_SUPPORT 327 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 328 329 /* NAND boot config */ 330 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 331 #define CONFIG_SYS_NAND_PAGE_COUNT 64 332 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 333 #define CONFIG_SYS_NAND_OOBSIZE 64 334 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 335 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 336 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 337 10, 11, 12, 13} 338 #define CONFIG_SYS_NAND_ECCSIZE 512 339 #define CONFIG_SYS_NAND_ECCBYTES 3 340 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 341 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 342 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 343 344 /* 345 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 346 * 64 bytes before this address should be set aside for u-boot.img's 347 * header. That is 0x800FFFC0--0x80100000 should not be used for any 348 * other needs. 349 */ 350 #define CONFIG_SYS_TEXT_BASE 0x80100000 351 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 352 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 353 354 #endif /* __CONFIG_H */ 355