1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_FSL_ELBC 18 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 19 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 20 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 21 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 22 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 23 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 24 25 #if defined(CONFIG_TARTGET_UCP1020T1) 26 27 #define CONFIG_UCP1020_REV_1_3 28 29 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 30 31 #define CONFIG_TSEC_ENET 32 #define CONFIG_TSEC1 33 #define CONFIG_TSEC3 34 #define CONFIG_HAS_ETH0 35 #define CONFIG_HAS_ETH1 36 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 37 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 38 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 39 #define CONFIG_IPADDR 10.80.41.229 40 #define CONFIG_SERVERIP 10.80.41.227 41 #define CONFIG_NETMASK 255.255.252.0 42 #define CONFIG_ETHPRIME "eTSEC3" 43 44 #ifndef CONFIG_SPI_FLASH 45 #endif 46 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 47 48 #define CONFIG_MMC 49 #define CONFIG_SYS_L2_SIZE (256 << 10) 50 51 #define CONFIG_LAST_STAGE_INIT 52 53 #endif 54 55 #if defined(CONFIG_TARGET_UCP1020) 56 57 #define CONFIG_UCP1020 58 #define CONFIG_UCP1020_REV_1_3 59 60 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 61 62 #define CONFIG_TSEC_ENET 63 #define CONFIG_TSEC1 64 #define CONFIG_TSEC2 65 #define CONFIG_TSEC3 66 #define CONFIG_HAS_ETH0 67 #define CONFIG_HAS_ETH1 68 #define CONFIG_HAS_ETH2 69 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 70 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 71 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 72 #define CONFIG_IPADDR 192.168.1.81 73 #define CONFIG_IPADDR1 192.168.1.82 74 #define CONFIG_IPADDR2 192.168.1.83 75 #define CONFIG_SERVERIP 192.168.1.80 76 #define CONFIG_GATEWAYIP 102.168.1.1 77 #define CONFIG_NETMASK 255.255.255.0 78 #define CONFIG_ETHPRIME "eTSEC1" 79 80 #ifndef CONFIG_SPI_FLASH 81 #endif 82 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 83 84 #define CONFIG_MMC 85 #define CONFIG_SYS_L2_SIZE (256 << 10) 86 87 #define CONFIG_LAST_STAGE_INIT 88 89 #endif 90 91 #ifdef CONFIG_SDCARD 92 #define CONFIG_RAMBOOT_SDCARD 93 #define CONFIG_SYS_RAMBOOT 94 #define CONFIG_SYS_EXTRA_ENV_RELOC 95 #define CONFIG_SYS_TEXT_BASE 0x11000000 96 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 97 #endif 98 99 #ifdef CONFIG_SPIFLASH 100 #define CONFIG_RAMBOOT_SPIFLASH 101 #define CONFIG_SYS_RAMBOOT 102 #define CONFIG_SYS_EXTRA_ENV_RELOC 103 #define CONFIG_SYS_TEXT_BASE 0x11000000 104 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 105 #endif 106 107 #ifndef CONFIG_SYS_TEXT_BASE 108 #define CONFIG_SYS_TEXT_BASE 0xeff80000 109 #endif 110 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 111 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 114 #endif 115 116 #ifndef CONFIG_SYS_MONITOR_BASE 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 118 #endif 119 120 /* High Level Configuration Options */ 121 #define CONFIG_BOOKE 122 #define CONFIG_E500 123 /* #define CONFIG_MPC85xx */ 124 125 #define CONFIG_MP 126 127 #define CONFIG_ENV_OVERWRITE 128 129 #define CONFIG_CMD_SATA 130 #define CONFIG_SATA_SIL 131 #define CONFIG_SYS_SATA_MAX_DEVICE 2 132 #define CONFIG_LIBATA 133 #define CONFIG_LBA48 134 135 #define CONFIG_SYS_CLK_FREQ 66666666 136 #define CONFIG_DDR_CLK_FREQ 66666666 137 138 #define CONFIG_HWCONFIG 139 140 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ 141 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ 142 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ 143 /* 144 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). 145 * there will be one entry in this array for each two (dummy) sensors in 146 * CONFIG_DTT_SENSORS. 147 * 148 * For uCP1020 module: 149 * - only one ADM1021/NCT72 150 * - i2c addr 0x41 151 * - conversion rate 0x02 = 0.25 conversions/second 152 * - ALERT output disabled 153 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg 154 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg 155 */ 156 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ 157 0x02, 0, 1, 0, 85, 1, 0, 85} } 158 159 #define CONFIG_CMD_DTT 160 161 /* 162 * These can be toggled for performance analysis, otherwise use default. 163 */ 164 #define CONFIG_L2_CACHE 165 #define CONFIG_BTB 166 167 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 168 169 #define CONFIG_ENABLE_36BIT_PHYS 170 171 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 172 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 173 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 174 175 #define CONFIG_SYS_CCSRBAR 0xffe00000 176 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 177 178 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 179 SPL code*/ 180 #ifdef CONFIG_SPL_BUILD 181 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 182 #endif 183 184 /* DDR Setup */ 185 #define CONFIG_DDR_ECC_ENABLE 186 #define CONFIG_SYS_FSL_DDR3 187 #ifndef CONFIG_DDR_ECC_ENABLE 188 #define CONFIG_SYS_DDR_RAW_TIMING 189 #define CONFIG_DDR_SPD 190 #endif 191 #define CONFIG_SYS_SPD_BUS_NUM 1 192 #undef CONFIG_FSL_DDR_INTERACTIVE 193 194 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 195 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 196 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 197 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 198 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 199 200 #define CONFIG_NUM_DDR_CONTROLLERS 1 201 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 202 203 /* Default settings for DDR3 */ 204 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 205 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 206 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 207 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 208 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 209 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 210 211 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 212 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 213 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 214 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 215 216 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 217 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 218 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 219 #define CONFIG_SYS_DDR_RCW_1 0x00000000 220 #define CONFIG_SYS_DDR_RCW_2 0x00000000 221 #ifdef CONFIG_DDR_ECC_ENABLE 222 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 223 #else 224 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 225 #endif 226 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 227 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 228 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 229 230 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 231 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 232 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 233 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 234 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 235 #define CONFIG_SYS_DDR_MODE_1 0x40461520 236 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 237 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 238 239 #undef CONFIG_CLOCKS_IN_MHZ 240 241 /* 242 * Memory map 243 * 244 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 245 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 246 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 247 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 248 * (early boot only) 249 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 250 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 251 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 252 */ 253 254 /* 255 * Local Bus Definitions 256 */ 257 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 258 #define CONFIG_SYS_FLASH_BASE 0xec000000 259 260 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 261 262 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 263 | BR_PS_16 | BR_V) 264 265 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 266 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 268 #define CONFIG_SYS_FLASH_QUIET_TEST 269 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 270 271 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 272 273 #undef CONFIG_SYS_FLASH_CHECKSUM 274 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 275 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 276 277 #define CONFIG_FLASH_CFI_DRIVER 278 #define CONFIG_SYS_FLASH_CFI 279 #define CONFIG_SYS_FLASH_EMPTY_INFO 280 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 281 282 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 283 284 #define CONFIG_SYS_INIT_RAM_LOCK 285 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 286 /* Initial L1 address */ 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 290 /* Size of used area in RAM */ 291 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 292 293 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 294 GENERATED_GBL_DATA_SIZE) 295 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 296 297 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 298 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 299 300 #define CONFIG_SYS_PMC_BASE 0xff980000 301 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 302 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 303 BR_PS_8 | BR_V) 304 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 305 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 306 OR_GPCM_EAD) 307 308 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 309 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 310 #ifdef CONFIG_NAND_FSL_ELBC 311 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 312 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 313 #endif 314 315 /* Serial Port - controlled on board with jumper J8 316 * open - index 2 317 * shorted - index 1 318 */ 319 #define CONFIG_CONS_INDEX 1 320 #undef CONFIG_SERIAL_SOFTWARE_FIFO 321 #define CONFIG_SYS_NS16550_SERIAL 322 #define CONFIG_SYS_NS16550_REG_SIZE 1 323 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 324 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 325 #define CONFIG_NS16550_MIN_FUNCTIONS 326 #endif 327 328 #define CONFIG_SYS_BAUDRATE_TABLE \ 329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 330 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 333 334 /* I2C */ 335 #define CONFIG_SYS_I2C 336 #define CONFIG_SYS_I2C_FSL 337 #define CONFIG_SYS_FSL_I2C_SPEED 400000 338 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 339 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 340 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 341 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 342 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 343 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 344 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 345 346 #define CONFIG_RTC_DS1337 347 #define CONFIG_SYS_RTC_DS1337_NOOSC 348 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 349 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 350 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 351 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 352 353 /* 354 * eSPI - Enhanced SPI 355 */ 356 #define CONFIG_HARD_SPI 357 358 #define CONFIG_SF_DEFAULT_SPEED 10000000 359 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 360 361 #if defined(CONFIG_PCI) 362 /* 363 * General PCI 364 * Memory space is mapped 1-1, but I/O space must start from 0. 365 */ 366 367 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 368 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 369 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 370 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 371 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 372 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 373 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 374 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 375 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 376 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 377 378 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 379 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 380 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 381 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 382 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 383 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 384 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 385 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 386 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 387 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 388 389 #define CONFIG_CMD_PCI 390 391 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 392 #define CONFIG_DOS_PARTITION 393 #endif /* CONFIG_PCI */ 394 395 /* 396 * Environment 397 */ 398 #ifdef CONFIG_ENV_FIT_UCBOOT 399 400 #define CONFIG_ENV_IS_IN_FLASH 401 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 402 #define CONFIG_ENV_SIZE 0x20000 403 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 404 405 #else 406 407 #define CONFIG_ENV_SPI_BUS 0 408 #define CONFIG_ENV_SPI_CS 0 409 #define CONFIG_ENV_SPI_MAX_HZ 10000000 410 #define CONFIG_ENV_SPI_MODE 0 411 412 #ifdef CONFIG_RAMBOOT_SPIFLASH 413 414 #define CONFIG_ENV_IS_IN_SPI_FLASH 415 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 416 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 417 #define CONFIG_ENV_SECT_SIZE 0x1000 418 419 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 420 /* Address and size of Redundant Environment Sector */ 421 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 422 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 423 #endif 424 425 #elif defined(CONFIG_RAMBOOT_SDCARD) 426 #define CONFIG_ENV_IS_IN_MMC 427 #define CONFIG_FSL_FIXED_MMC_LOCATION 428 #define CONFIG_ENV_SIZE 0x2000 429 #define CONFIG_SYS_MMC_ENV_DEV 0 430 431 #elif defined(CONFIG_SYS_RAMBOOT) 432 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 433 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 434 #define CONFIG_ENV_SIZE 0x2000 435 436 #else 437 #define CONFIG_ENV_IS_IN_FLASH 438 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 439 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 440 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 441 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 442 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 443 /* Address and size of Redundant Environment Sector */ 444 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 445 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 446 #endif 447 448 #endif 449 450 #endif /* CONFIG_ENV_FIT_UCBOOT */ 451 452 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 454 455 /* 456 * Command line configuration. 457 */ 458 #define CONFIG_CMD_IRQ 459 #define CONFIG_CMD_DATE 460 #define CONFIG_CMD_IRQ 461 #define CONFIG_CMD_REGINFO 462 #define CONFIG_CMD_ERRATA 463 #define CONFIG_CMD_CRAMFS 464 465 /* 466 * USB 467 */ 468 #define CONFIG_HAS_FSL_DR_USB 469 470 #if defined(CONFIG_HAS_FSL_DR_USB) 471 #define CONFIG_USB_EHCI 472 473 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 474 475 #ifdef CONFIG_USB_EHCI 476 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 477 #define CONFIG_USB_EHCI_FSL 478 #endif 479 #endif 480 481 #undef CONFIG_WATCHDOG /* watchdog disabled */ 482 483 #ifdef CONFIG_MMC 484 #define CONFIG_FSL_ESDHC 485 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 486 #define CONFIG_MMC_SPI 487 #define CONFIG_CMD_MMC_SPI 488 #define CONFIG_GENERIC_MMC 489 #endif 490 491 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) 492 #define CONFIG_DOS_PARTITION 493 #endif 494 495 /* Misc Extra Settings */ 496 #undef CONFIG_WATCHDOG /* watchdog disabled */ 497 498 /* 499 * Miscellaneous configurable options 500 */ 501 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 502 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 503 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 504 #if defined(CONFIG_CMD_KGDB) 505 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 506 #else 507 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 508 #endif 509 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 510 /* Print Buffer Size */ 511 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 512 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 513 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 514 515 /* 516 * For booting Linux, the board info and command line data 517 * have to be in the first 64 MB of memory, since this is 518 * the maximum mapped by the Linux kernel during initialization. 519 */ 520 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 521 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 522 523 #if defined(CONFIG_CMD_KGDB) 524 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 525 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 526 #endif 527 528 /* 529 * Environment Configuration 530 */ 531 532 #if defined(CONFIG_TSEC_ENET) 533 534 #if defined(CONFIG_UCP1020_REV_1_2) 535 #define CONFIG_PHY_MICREL_KSZ9021 536 #elif defined(CONFIG_UCP1020_REV_1_3) 537 #define CONFIG_PHY_MICREL_KSZ9031 538 #else 539 #error "UCP1020 module revision is not defined !!!" 540 #endif 541 542 #define CONFIG_BOOTP_SERVERIP 543 544 #define CONFIG_MII /* MII PHY management */ 545 #define CONFIG_TSEC1_NAME "eTSEC1" 546 #define CONFIG_TSEC2_NAME "eTSEC2" 547 #define CONFIG_TSEC3_NAME "eTSEC3" 548 549 #define TSEC1_PHY_ADDR 4 550 #define TSEC2_PHY_ADDR 0 551 #define TSEC2_PHY_ADDR_SGMII 0x00 552 #define TSEC3_PHY_ADDR 6 553 554 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 555 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 556 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 557 558 #define TSEC1_PHYIDX 0 559 #define TSEC2_PHYIDX 0 560 #define TSEC3_PHYIDX 0 561 562 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 563 564 #endif 565 566 #define CONFIG_HOSTNAME UCP1020 567 #define CONFIG_ROOTPATH "/opt/nfsroot" 568 #define CONFIG_BOOTFILE "uImage" 569 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 570 571 /* default location for tftp and bootm */ 572 #define CONFIG_LOADADDR 1000000 573 574 #define CONFIG_BOOTARGS /* the boot command will set bootargs */ 575 576 #define CONFIG_BAUDRATE 115200 577 578 #if defined(CONFIG_DONGLE) 579 580 #define CONFIG_EXTRA_ENV_SETTINGS \ 581 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 582 "bootfile=uImage\0" \ 583 "consoledev=ttyS0\0" \ 584 "cramfsfile=image.cramfs\0" \ 585 "dtbaddr=0x00c00000\0" \ 586 "dtbfile=image.dtb\0" \ 587 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 588 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 589 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 590 "fileaddr=0x01000000\0" \ 591 "filesize=0x00080000\0" \ 592 "flashmbr=sf probe 0; " \ 593 "tftp $loadaddr $mbr; " \ 594 "sf erase $mbr_offset +$filesize; " \ 595 "sf write $loadaddr $mbr_offset $filesize\0" \ 596 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 597 "protect off $nor_recoveryaddr +$filesize; " \ 598 "erase $nor_recoveryaddr +$filesize; " \ 599 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 600 "protect on $nor_recoveryaddr +$filesize\0 " \ 601 "flashuboot=tftp $ubootaddr $ubootfile; " \ 602 "protect off $nor_ubootaddr +$filesize; " \ 603 "erase $nor_ubootaddr +$filesize; " \ 604 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 605 "protect on $nor_ubootaddr +$filesize\0 " \ 606 "flashworking=tftp $workingaddr $cramfsfile; " \ 607 "protect off $nor_workingaddr +$filesize; " \ 608 "erase $nor_workingaddr +$filesize; " \ 609 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 610 "protect on $nor_workingaddr +$filesize\0 " \ 611 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 612 "kerneladdr=0x01100000\0" \ 613 "kernelfile=uImage\0" \ 614 "loadaddr=0x01000000\0" \ 615 "mbr=uCP1020d.mbr\0" \ 616 "mbr_offset=0x00000000\0" \ 617 "mmbr=uCP1020Quiet.mbr\0" \ 618 "mmcpart=0:2\0" \ 619 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 620 "mmc erase 1 1; " \ 621 "mmc write $loadaddr 1 1\0" \ 622 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 623 "mmc erase 0x40 0x400; " \ 624 "mmc write $loadaddr 0x40 0x400\0" \ 625 "netdev=eth0\0" \ 626 "nor_recoveryaddr=0xEC0A0000\0" \ 627 "nor_ubootaddr=0xEFF80000\0" \ 628 "nor_workingaddr=0xECFA0000\0" \ 629 "norbootrecovery=setenv bootargs $recoverybootargs" \ 630 " console=$consoledev,$baudrate $othbootargs; " \ 631 "run norloadrecovery; " \ 632 "bootm $kerneladdr - $dtbaddr\0" \ 633 "norbootworking=setenv bootargs $workingbootargs" \ 634 " console=$consoledev,$baudrate $othbootargs; " \ 635 "run norloadworking; " \ 636 "bootm $kerneladdr - $dtbaddr\0" \ 637 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 638 "setenv cramfsaddr $nor_recoveryaddr; " \ 639 "cramfsload $dtbaddr $dtbfile; " \ 640 "cramfsload $kerneladdr $kernelfile\0" \ 641 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 642 "setenv cramfsaddr $nor_workingaddr; " \ 643 "cramfsload $dtbaddr $dtbfile; " \ 644 "cramfsload $kerneladdr $kernelfile\0" \ 645 "prog_spi_mbr=run spi__mbr\0" \ 646 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 647 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 648 "run spi__cramfs\0" \ 649 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 650 " console=$consoledev,$baudrate $othbootargs; " \ 651 "tftp $rootfsaddr $rootfsfile; " \ 652 "tftp $loadaddr $kernelfile; " \ 653 "tftp $dtbaddr $dtbfile; " \ 654 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 655 "ramdisk_size=120000\0" \ 656 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 657 "recoveryaddr=0x02F00000\0" \ 658 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 659 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 660 "mw.l 0xffe0f008 0x00400000\0" \ 661 "rootfsaddr=0x02F00000\0" \ 662 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 663 "rootpath=/opt/nfsroot\0" \ 664 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 665 "protect off 0xeC000000 +$filesize; " \ 666 "erase 0xEC000000 +$filesize; " \ 667 "cp.b $loadaddr 0xEC000000 $filesize; " \ 668 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 669 "protect on 0xeC000000 +$filesize\0" \ 670 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 671 "protect off 0xeFF80000 +$filesize; " \ 672 "erase 0xEFF80000 +$filesize; " \ 673 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 674 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 675 "protect on 0xeFF80000 +$filesize\0" \ 676 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 677 "sf probe 0; sf erase 0x8000 +$filesize; " \ 678 "sf write $loadaddr 0x8000 $filesize\0" \ 679 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 680 "protect off 0xec0a0000 +$filesize; " \ 681 "erase 0xeC0A0000 +$filesize; " \ 682 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 683 "protect on 0xec0a0000 +$filesize\0" \ 684 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 685 "sf probe 1; sf erase 0 +$filesize; " \ 686 "sf write $loadaddr 0 $filesize\0" \ 687 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 688 "sf probe 0; sf erase 0 +$filesize; " \ 689 "sf write $loadaddr 0 $filesize\0" \ 690 "tftpflash=tftpboot $loadaddr $uboot; " \ 691 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 692 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 693 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 694 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 695 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 696 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 697 "ubootaddr=0x01000000\0" \ 698 "ubootfile=u-boot.bin\0" \ 699 "ubootd=u-boot4dongle.bin\0" \ 700 "upgrade=run flashworking\0" \ 701 "usb_phy_type=ulpi\0 " \ 702 "workingaddr=0x02F00000\0" \ 703 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 704 705 #else 706 707 #if defined(CONFIG_UCP1020T1) 708 709 #define CONFIG_EXTRA_ENV_SETTINGS \ 710 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 711 "bootfile=uImage\0" \ 712 "consoledev=ttyS0\0" \ 713 "cramfsfile=image.cramfs\0" \ 714 "dtbaddr=0x00c00000\0" \ 715 "dtbfile=image.dtb\0" \ 716 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 717 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 718 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 719 "fileaddr=0x01000000\0" \ 720 "filesize=0x00080000\0" \ 721 "flashmbr=sf probe 0; " \ 722 "tftp $loadaddr $mbr; " \ 723 "sf erase $mbr_offset +$filesize; " \ 724 "sf write $loadaddr $mbr_offset $filesize\0" \ 725 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 726 "protect off $nor_recoveryaddr +$filesize; " \ 727 "erase $nor_recoveryaddr +$filesize; " \ 728 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 729 "protect on $nor_recoveryaddr +$filesize\0 " \ 730 "flashuboot=tftp $ubootaddr $ubootfile; " \ 731 "protect off $nor_ubootaddr +$filesize; " \ 732 "erase $nor_ubootaddr +$filesize; " \ 733 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 734 "protect on $nor_ubootaddr +$filesize\0 " \ 735 "flashworking=tftp $workingaddr $cramfsfile; " \ 736 "protect off $nor_workingaddr +$filesize; " \ 737 "erase $nor_workingaddr +$filesize; " \ 738 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 739 "protect on $nor_workingaddr +$filesize\0 " \ 740 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 741 "kerneladdr=0x01100000\0" \ 742 "kernelfile=uImage\0" \ 743 "loadaddr=0x01000000\0" \ 744 "mbr=uCP1020.mbr\0" \ 745 "mbr_offset=0x00000000\0" \ 746 "netdev=eth0\0" \ 747 "nor_recoveryaddr=0xEC0A0000\0" \ 748 "nor_ubootaddr=0xEFF80000\0" \ 749 "nor_workingaddr=0xECFA0000\0" \ 750 "norbootrecovery=setenv bootargs $recoverybootargs" \ 751 " console=$consoledev,$baudrate $othbootargs; " \ 752 "run norloadrecovery; " \ 753 "bootm $kerneladdr - $dtbaddr\0" \ 754 "norbootworking=setenv bootargs $workingbootargs" \ 755 " console=$consoledev,$baudrate $othbootargs; " \ 756 "run norloadworking; " \ 757 "bootm $kerneladdr - $dtbaddr\0" \ 758 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 759 "setenv cramfsaddr $nor_recoveryaddr; " \ 760 "cramfsload $dtbaddr $dtbfile; " \ 761 "cramfsload $kerneladdr $kernelfile\0" \ 762 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 763 "setenv cramfsaddr $nor_workingaddr; " \ 764 "cramfsload $dtbaddr $dtbfile; " \ 765 "cramfsload $kerneladdr $kernelfile\0" \ 766 "othbootargs=quiet\0" \ 767 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 768 " console=$consoledev,$baudrate $othbootargs; " \ 769 "tftp $rootfsaddr $rootfsfile; " \ 770 "tftp $loadaddr $kernelfile; " \ 771 "tftp $dtbaddr $dtbfile; " \ 772 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 773 "ramdisk_size=120000\0" \ 774 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 775 "recoveryaddr=0x02F00000\0" \ 776 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 777 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 778 "mw.l 0xffe0f008 0x00400000\0" \ 779 "rootfsaddr=0x02F00000\0" \ 780 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 781 "rootpath=/opt/nfsroot\0" \ 782 "silent=1\0" \ 783 "tftpflash=tftpboot $loadaddr $uboot; " \ 784 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 785 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 786 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 787 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 788 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 789 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 790 "ubootaddr=0x01000000\0" \ 791 "ubootfile=u-boot.bin\0" \ 792 "upgrade=run flashworking\0" \ 793 "workingaddr=0x02F00000\0" \ 794 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 795 796 #else /* For Arcturus Modules */ 797 798 #define CONFIG_EXTRA_ENV_SETTINGS \ 799 "bootcmd=run norkernel\0" \ 800 "bootfile=uImage\0" \ 801 "consoledev=ttyS0\0" \ 802 "dtbaddr=0x00c00000\0" \ 803 "dtbfile=image.dtb\0" \ 804 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 805 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 806 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 807 "fileaddr=0x01000000\0" \ 808 "filesize=0x00080000\0" \ 809 "flashmbr=sf probe 0; " \ 810 "tftp $loadaddr $mbr; " \ 811 "sf erase $mbr_offset +$filesize; " \ 812 "sf write $loadaddr $mbr_offset $filesize\0" \ 813 "flashuboot=tftp $loadaddr $ubootfile; " \ 814 "protect off $nor_ubootaddr0 +$filesize; " \ 815 "erase $nor_ubootaddr0 +$filesize; " \ 816 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 817 "protect on $nor_ubootaddr0 +$filesize; " \ 818 "protect off $nor_ubootaddr1 +$filesize; " \ 819 "erase $nor_ubootaddr1 +$filesize; " \ 820 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 821 "protect on $nor_ubootaddr1 +$filesize\0 " \ 822 "format0=protect off $part0base +$part0size; " \ 823 "erase $part0base +$part0size\0" \ 824 "format1=protect off $part1base +$part1size; " \ 825 "erase $part1base +$part1size\0" \ 826 "format2=protect off $part2base +$part2size; " \ 827 "erase $part2base +$part2size\0" \ 828 "format3=protect off $part3base +$part3size; " \ 829 "erase $part3base +$part3size\0" \ 830 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 831 "kerneladdr=0x01100000\0" \ 832 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 833 "kernelfile=uImage\0" \ 834 "loadaddr=0x01000000\0" \ 835 "mbr=uCP1020.mbr\0" \ 836 "mbr_offset=0x00000000\0" \ 837 "netdev=eth0\0" \ 838 "nor_ubootaddr0=0xEC000000\0" \ 839 "nor_ubootaddr1=0xEFF80000\0" \ 840 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 841 "run norkernelload; " \ 842 "bootm $kerneladdr - $dtbaddr\0" \ 843 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 844 "setenv cramfsaddr $part0base; " \ 845 "cramfsload $dtbaddr $dtbfile; " \ 846 "cramfsload $kerneladdr $kernelfile\0" \ 847 "part0base=0xEC100000\0" \ 848 "part0size=0x00700000\0" \ 849 "part1base=0xEC800000\0" \ 850 "part1size=0x02000000\0" \ 851 "part2base=0xEE800000\0" \ 852 "part2size=0x00800000\0" \ 853 "part3base=0xEF000000\0" \ 854 "part3size=0x00F80000\0" \ 855 "partENVbase=0xEC080000\0" \ 856 "partENVsize=0x00080000\0" \ 857 "program0=tftp part0-000000.bin; " \ 858 "protect off $part0base +$filesize; " \ 859 "erase $part0base +$filesize; " \ 860 "cp.b $loadaddr $part0base $filesize; " \ 861 "echo Verifying...; " \ 862 "cmp.b $loadaddr $part0base $filesize\0" \ 863 "program1=tftp part1-000000.bin; " \ 864 "protect off $part1base +$filesize; " \ 865 "erase $part1base +$filesize; " \ 866 "cp.b $loadaddr $part1base $filesize; " \ 867 "echo Verifying...; " \ 868 "cmp.b $loadaddr $part1base $filesize\0" \ 869 "program2=tftp part2-000000.bin; " \ 870 "protect off $part2base +$filesize; " \ 871 "erase $part2base +$filesize; " \ 872 "cp.b $loadaddr $part2base $filesize; " \ 873 "echo Verifying...; " \ 874 "cmp.b $loadaddr $part2base $filesize\0" \ 875 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 876 " console=$consoledev,$baudrate $othbootargs; " \ 877 "tftp $rootfsaddr $rootfsfile; " \ 878 "tftp $loadaddr $kernelfile; " \ 879 "tftp $dtbaddr $dtbfile; " \ 880 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 881 "ramdisk_size=120000\0" \ 882 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 883 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 884 "mw.l 0xffe0f008 0x00400000\0" \ 885 "rootfsaddr=0x02F00000\0" \ 886 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 887 "rootpath=/opt/nfsroot\0" \ 888 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 889 "sf probe 0; sf erase 0 +$filesize; " \ 890 "sf write $loadaddr 0 $filesize\0" \ 891 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 892 "protect off 0xeC000000 +$filesize; " \ 893 "erase 0xEC000000 +$filesize; " \ 894 "cp.b $loadaddr 0xEC000000 $filesize; " \ 895 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 896 "protect on 0xeC000000 +$filesize\0" \ 897 "tftpflash=tftpboot $loadaddr $uboot; " \ 898 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 899 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 900 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 901 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 902 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 903 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 904 "ubootfile=u-boot.bin\0" \ 905 "upgrade=run flashuboot\0" \ 906 "usb_phy_type=ulpi\0 " \ 907 "boot_nfs= " \ 908 "setenv bootargs root=/dev/nfs rw " \ 909 "nfsroot=$serverip:$rootpath " \ 910 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 911 "console=$consoledev,$baudrate $othbootargs;" \ 912 "tftp $loadaddr $bootfile;" \ 913 "tftp $fdtaddr $fdtfile;" \ 914 "bootm $loadaddr - $fdtaddr\0" \ 915 "boot_hd = " \ 916 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 917 "console=$consoledev,$baudrate $othbootargs;" \ 918 "usb start;" \ 919 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 920 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 921 "bootm $loadaddr - $fdtaddr\0" \ 922 "boot_usb_fat = " \ 923 "setenv bootargs root=/dev/ram rw " \ 924 "console=$consoledev,$baudrate $othbootargs " \ 925 "ramdisk_size=$ramdisk_size;" \ 926 "usb start;" \ 927 "fatload usb 0:2 $loadaddr $bootfile;" \ 928 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 929 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 930 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 931 "boot_usb_ext2 = " \ 932 "setenv bootargs root=/dev/ram rw " \ 933 "console=$consoledev,$baudrate $othbootargs " \ 934 "ramdisk_size=$ramdisk_size;" \ 935 "usb start;" \ 936 "ext2load usb 0:4 $loadaddr $bootfile;" \ 937 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 938 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 939 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 940 "boot_nor = " \ 941 "setenv bootargs root=/dev/$jffs2nor rw " \ 942 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 943 "bootm $norbootaddr - $norfdtaddr\0 " \ 944 "boot_ram = " \ 945 "setenv bootargs root=/dev/ram rw " \ 946 "console=$consoledev,$baudrate $othbootargs " \ 947 "ramdisk_size=$ramdisk_size;" \ 948 "tftp $ramdiskaddr $ramdiskfile;" \ 949 "tftp $loadaddr $bootfile;" \ 950 "tftp $fdtaddr $fdtfile;" \ 951 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 952 953 #endif 954 #endif 955 956 #endif /* __CONFIG_H */ 957