1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 46 #define CONFIG_SPL_ENV_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_SPL_LIBGENERIC_SUPPORT 51 #define CONFIG_SPL_LIBCOMMON_SUPPORT 52 #define CONFIG_SPL_I2C_SUPPORT 53 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 54 #define CONFIG_FSL_LAW /* Use common FSL init code */ 55 #define CONFIG_SYS_TEXT_BASE 0x00201000 56 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 57 #define CONFIG_SPL_PAD_TO 0x40000 58 #define CONFIG_SPL_MAX_SIZE 0x28000 59 #define RESET_VECTOR_OFFSET 0x27FFC 60 #define BOOT_PAGE_OFFSET 0x27000 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #ifdef CONFIG_NAND 69 #define CONFIG_SPL_NAND_SUPPORT 70 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 72 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 73 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 75 #define CONFIG_SPL_NAND_BOOT 76 #endif 77 78 #ifdef CONFIG_SPIFLASH 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 80 #define CONFIG_SPL_SPI_SUPPORT 81 #define CONFIG_SPL_SPI_FLASH_SUPPORT 82 #define CONFIG_SPL_SPI_FLASH_MINIMAL 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 88 #ifndef CONFIG_SPL_BUILD 89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 90 #endif 91 #define CONFIG_SPL_SPI_BOOT 92 #endif 93 94 #ifdef CONFIG_SDCARD 95 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 96 #define CONFIG_SPL_MMC_SUPPORT 97 #define CONFIG_SPL_MMC_MINIMAL 98 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 99 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 100 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 101 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 102 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 103 #ifndef CONFIG_SPL_BUILD 104 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 105 #endif 106 #define CONFIG_SPL_MMC_BOOT 107 #endif 108 109 #endif /* CONFIG_RAMBOOT_PBL */ 110 111 #define CONFIG_SRIO_PCIE_BOOT_MASTER 112 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 113 /* Set 1M boot space */ 114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 116 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 117 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 118 #define CONFIG_SYS_NO_FLASH 119 #endif 120 121 #ifndef CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_TEXT_BASE 0xeff40000 123 #endif 124 125 #ifndef CONFIG_RESET_VECTOR_ADDRESS 126 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 127 #endif 128 129 /* 130 * These can be toggled for performance analysis, otherwise use default. 131 */ 132 #define CONFIG_SYS_CACHE_STASHING 133 #define CONFIG_BTB /* toggle branch predition */ 134 #define CONFIG_DDR_ECC 135 #ifdef CONFIG_DDR_ECC 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 137 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 138 #endif 139 140 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 141 #define CONFIG_SYS_MEMTEST_END 0x00400000 142 #define CONFIG_SYS_ALT_MEMTEST 143 144 #ifndef CONFIG_SYS_NO_FLASH 145 #define CONFIG_FLASH_CFI_DRIVER 146 #define CONFIG_SYS_FLASH_CFI 147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 148 #endif 149 150 #if defined(CONFIG_SPIFLASH) 151 #define CONFIG_SYS_EXTRA_ENV_RELOC 152 #define CONFIG_ENV_IS_IN_SPI_FLASH 153 #define CONFIG_ENV_SPI_BUS 0 154 #define CONFIG_ENV_SPI_CS 0 155 #define CONFIG_ENV_SPI_MAX_HZ 10000000 156 #define CONFIG_ENV_SPI_MODE 0 157 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 158 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 159 #define CONFIG_ENV_SECT_SIZE 0x10000 160 #elif defined(CONFIG_SDCARD) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_MMC 163 #define CONFIG_SYS_MMC_ENV_DEV 0 164 #define CONFIG_ENV_SIZE 0x2000 165 #define CONFIG_ENV_OFFSET (512 * 0x800) 166 #elif defined(CONFIG_NAND) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_ENV_IS_IN_NAND 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 171 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 172 #define CONFIG_ENV_IS_IN_REMOTE 173 #define CONFIG_ENV_ADDR 0xffe20000 174 #define CONFIG_ENV_SIZE 0x2000 175 #elif defined(CONFIG_ENV_IS_NOWHERE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #else 178 #define CONFIG_ENV_IS_IN_FLASH 179 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 180 #define CONFIG_ENV_SIZE 0x2000 181 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 182 #endif 183 184 #ifndef __ASSEMBLY__ 185 unsigned long get_board_sys_clk(void); 186 unsigned long get_board_ddr_clk(void); 187 #endif 188 189 #define CONFIG_SYS_CLK_FREQ 66660000 190 #define CONFIG_DDR_CLK_FREQ 133330000 191 192 /* 193 * Config the L3 Cache as L3 SRAM 194 */ 195 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 196 #define CONFIG_SYS_L3_SIZE (512 << 10) 197 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 198 #ifdef CONFIG_RAMBOOT_PBL 199 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 200 #endif 201 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 202 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 203 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 204 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 205 206 #define CONFIG_SYS_DCSRBAR 0xf0000000 207 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 208 209 /* EEPROM */ 210 #define CONFIG_ID_EEPROM 211 #define CONFIG_SYS_I2C_EEPROM_NXID 212 #define CONFIG_SYS_EEPROM_BUS_NUM 0 213 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 215 216 /* 217 * DDR Setup 218 */ 219 #define CONFIG_VERY_BIG_RAM 220 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 221 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 222 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 223 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 224 #define CONFIG_DDR_SPD 225 #define CONFIG_SYS_FSL_DDR3 226 #undef CONFIG_FSL_DDR_INTERACTIVE 227 #define CONFIG_SYS_SPD_BUS_NUM 0 228 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 229 #define SPD_EEPROM_ADDRESS1 0x51 230 #define SPD_EEPROM_ADDRESS2 0x52 231 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 232 #define CTRL_INTLV_PREFERED cacheline 233 234 /* 235 * IFC Definitions 236 */ 237 #define CONFIG_SYS_FLASH_BASE 0xe8000000 238 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 239 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 240 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 241 CSPR_PORT_SIZE_16 | \ 242 CSPR_MSEL_NOR | \ 243 CSPR_V) 244 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 245 246 /* NOR Flash Timing Params */ 247 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 248 249 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 250 FTIM0_NOR_TEADC(0x5) | \ 251 FTIM0_NOR_TEAHC(0x5)) 252 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 253 FTIM1_NOR_TRAD_NOR(0x1A) |\ 254 FTIM1_NOR_TSEQRAD_NOR(0x13)) 255 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 256 FTIM2_NOR_TCH(0x4) | \ 257 FTIM2_NOR_TWPH(0x0E) | \ 258 FTIM2_NOR_TWP(0x1c)) 259 #define CONFIG_SYS_NOR_FTIM3 0x0 260 261 #define CONFIG_SYS_FLASH_QUIET_TEST 262 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 263 264 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 265 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 266 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 267 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 268 #define CONFIG_SYS_FLASH_EMPTY_INFO 269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 270 271 /* CPLD on IFC */ 272 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 273 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 274 #define CONFIG_SYS_CSPR2_EXT (0xf) 275 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 276 | CSPR_PORT_SIZE_8 \ 277 | CSPR_MSEL_GPCM \ 278 | CSPR_V) 279 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 280 #define CONFIG_SYS_CSOR2 0x0 281 282 /* CPLD Timing parameters for IFC CS2 */ 283 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 284 FTIM0_GPCM_TEADC(0x0e) | \ 285 FTIM0_GPCM_TEAHC(0x0e)) 286 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 287 FTIM1_GPCM_TRAD(0x1f)) 288 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 289 FTIM2_GPCM_TCH(0x8) | \ 290 FTIM2_GPCM_TWP(0x1f)) 291 #define CONFIG_SYS_CS2_FTIM3 0x0 292 293 /* NAND Flash on IFC */ 294 #define CONFIG_NAND_FSL_IFC 295 #define CONFIG_SYS_NAND_BASE 0xff800000 296 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 297 298 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 299 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 300 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 301 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 302 | CSPR_V) 303 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 304 305 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 306 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 307 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 308 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 309 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 310 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 311 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 312 313 #define CONFIG_SYS_NAND_ONFI_DETECTION 314 315 /* ONFI NAND Flash mode0 Timing Params */ 316 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 317 FTIM0_NAND_TWP(0x18) | \ 318 FTIM0_NAND_TWCHT(0x07) | \ 319 FTIM0_NAND_TWH(0x0a)) 320 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 321 FTIM1_NAND_TWBE(0x39) | \ 322 FTIM1_NAND_TRR(0x0e) | \ 323 FTIM1_NAND_TRP(0x18)) 324 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 325 FTIM2_NAND_TREH(0x0a) | \ 326 FTIM2_NAND_TWHRE(0x1e)) 327 #define CONFIG_SYS_NAND_FTIM3 0x0 328 329 #define CONFIG_SYS_NAND_DDR_LAW 11 330 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 331 #define CONFIG_SYS_MAX_NAND_DEVICE 1 332 #define CONFIG_CMD_NAND 333 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 334 335 #if defined(CONFIG_NAND) 336 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 344 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 345 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 346 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 347 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 348 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 349 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 350 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 351 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 352 #else 353 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 361 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 362 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 363 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 364 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 365 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 366 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 367 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 368 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 369 #endif 370 371 #if defined(CONFIG_RAMBOOT_PBL) 372 #define CONFIG_SYS_RAMBOOT 373 #endif 374 375 #ifdef CONFIG_SPL_BUILD 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 377 #else 378 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 379 #endif 380 381 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 382 #define CONFIG_MISC_INIT_R 383 #define CONFIG_HWCONFIG 384 385 /* define to use L1 as initial stack */ 386 #define CONFIG_L1_INIT_RAM 387 #define CONFIG_SYS_INIT_RAM_LOCK 388 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 391 /* The assembler doesn't like typecast */ 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 393 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 394 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 395 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 396 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 397 GENERATED_GBL_DATA_SIZE) 398 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 399 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 400 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 401 402 /* 403 * Serial Port 404 */ 405 #define CONFIG_CONS_INDEX 1 406 #define CONFIG_SYS_NS16550_SERIAL 407 #define CONFIG_SYS_NS16550_REG_SIZE 1 408 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 409 #define CONFIG_SYS_BAUDRATE_TABLE \ 410 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 411 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 412 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 413 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 414 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 415 416 /* 417 * I2C 418 */ 419 #define CONFIG_SYS_I2C 420 #define CONFIG_SYS_I2C_FSL 421 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 422 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 425 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 426 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 427 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 428 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 429 #define CONFIG_SYS_FSL_I2C_SPEED 100000 430 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 431 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 432 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 433 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 434 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 435 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 436 #define I2C_MUX_CH_DEFAULT 0x8 437 438 #define I2C_MUX_CH_VOL_MONITOR 0xa 439 440 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 441 #ifndef CONFIG_SPL_BUILD 442 #define CONFIG_VID 443 #endif 444 #define CONFIG_VOL_MONITOR_IR36021_SET 445 #define CONFIG_VOL_MONITOR_IR36021_READ 446 /* The lowest and highest voltage allowed for T208xRDB */ 447 #define VDD_MV_MIN 819 448 #define VDD_MV_MAX 1212 449 450 /* 451 * RapidIO 452 */ 453 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 454 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 455 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 456 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 457 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 458 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 459 /* 460 * for slave u-boot IMAGE instored in master memory space, 461 * PHYS must be aligned based on the SIZE 462 */ 463 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 467 /* 468 * for slave UCODE and ENV instored in master memory space, 469 * PHYS must be aligned based on the SIZE 470 */ 471 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 472 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 474 475 /* slave core release by master*/ 476 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 477 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 478 479 /* 480 * SRIO_PCIE_BOOT - SLAVE 481 */ 482 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 483 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 484 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 485 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 486 #endif 487 488 /* 489 * eSPI - Enhanced SPI 490 */ 491 #ifdef CONFIG_SPI_FLASH 492 #define CONFIG_SPI_FLASH_BAR 493 #define CONFIG_SF_DEFAULT_SPEED 10000000 494 #define CONFIG_SF_DEFAULT_MODE 0 495 #endif 496 497 /* 498 * General PCI 499 * Memory space is mapped 1-1, but I/O space must start from 0. 500 */ 501 #define CONFIG_PCI /* Enable PCI/PCIE */ 502 #define CONFIG_PCIE1 /* PCIE controller 1 */ 503 #define CONFIG_PCIE2 /* PCIE controller 2 */ 504 #define CONFIG_PCIE3 /* PCIE controller 3 */ 505 #define CONFIG_PCIE4 /* PCIE controller 4 */ 506 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 507 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 508 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 509 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 510 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 511 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 512 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 513 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 514 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 516 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 517 518 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 519 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 520 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 521 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 522 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 523 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 524 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 525 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 526 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 527 528 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 529 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 530 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 531 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 532 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 533 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 534 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 535 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 536 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 537 538 /* controller 4, Base address 203000 */ 539 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 540 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 541 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 542 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 543 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 544 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 545 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 546 547 #ifdef CONFIG_PCI 548 #define CONFIG_PCI_INDIRECT_BRIDGE 549 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 550 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 551 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 552 #define CONFIG_DOS_PARTITION 553 #endif 554 555 /* Qman/Bman */ 556 #ifndef CONFIG_NOBQFMAN 557 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 558 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 559 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 560 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 561 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 562 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 563 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 564 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 565 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 566 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 567 CONFIG_SYS_BMAN_CENA_SIZE) 568 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 569 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 570 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 571 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 572 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 573 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 574 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 575 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 576 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 577 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 578 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 579 CONFIG_SYS_QMAN_CENA_SIZE) 580 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 581 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 582 583 #define CONFIG_SYS_DPAA_FMAN 584 #define CONFIG_SYS_DPAA_PME 585 #define CONFIG_SYS_PMAN 586 #define CONFIG_SYS_DPAA_DCE 587 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 588 #define CONFIG_SYS_INTERLAKEN 589 590 /* Default address of microcode for the Linux Fman driver */ 591 #if defined(CONFIG_SPIFLASH) 592 /* 593 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 594 * env, so we got 0x110000. 595 */ 596 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 597 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 598 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 599 #define CONFIG_CORTINA_FW_ADDR 0x120000 600 601 #elif defined(CONFIG_SDCARD) 602 /* 603 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 604 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 605 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 606 */ 607 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 608 #define CONFIG_SYS_CORTINA_FW_IN_MMC 609 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 610 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 611 612 #elif defined(CONFIG_NAND) 613 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 614 #define CONFIG_SYS_CORTINA_FW_IN_NAND 615 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 616 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 617 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 618 /* 619 * Slave has no ucode locally, it can fetch this from remote. When implementing 620 * in two corenet boards, slave's ucode could be stored in master's memory 621 * space, the address can be mapped from slave TLB->slave LAW-> 622 * slave SRIO or PCIE outbound window->master inbound window-> 623 * master LAW->the ucode address in master's memory space. 624 */ 625 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 626 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 627 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 628 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 629 #else 630 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 631 #define CONFIG_SYS_CORTINA_FW_IN_NOR 632 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 633 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 634 #endif 635 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 636 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 637 #endif /* CONFIG_NOBQFMAN */ 638 639 #ifdef CONFIG_SYS_DPAA_FMAN 640 #define CONFIG_FMAN_ENET 641 #define CONFIG_PHYLIB_10G 642 #define CONFIG_PHY_AQUANTIA 643 #define CONFIG_PHY_CORTINA 644 #define CONFIG_PHY_REALTEK 645 #define CONFIG_CORTINA_FW_LENGTH 0x40000 646 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 647 #define RGMII_PHY2_ADDR 0x02 648 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 649 #define CORTINA_PHY_ADDR2 0x0d 650 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 651 #define FM1_10GEC4_PHY_ADDR 0x01 652 #endif 653 654 #ifdef CONFIG_FMAN_ENET 655 #define CONFIG_MII /* MII PHY management */ 656 #define CONFIG_ETHPRIME "FM1@DTSEC3" 657 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 658 #endif 659 660 /* 661 * SATA 662 */ 663 #ifdef CONFIG_FSL_SATA_V2 664 #define CONFIG_LIBATA 665 #define CONFIG_FSL_SATA 666 #define CONFIG_SYS_SATA_MAX_DEVICE 2 667 #define CONFIG_SATA1 668 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 669 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 670 #define CONFIG_SATA2 671 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 672 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 673 #define CONFIG_LBA48 674 #define CONFIG_CMD_SATA 675 #define CONFIG_DOS_PARTITION 676 #endif 677 678 /* 679 * USB 680 */ 681 #ifdef CONFIG_USB_EHCI 682 #define CONFIG_USB_STORAGE 683 #define CONFIG_USB_EHCI_FSL 684 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 685 #define CONFIG_HAS_FSL_DR_USB 686 #endif 687 688 /* 689 * SDHC 690 */ 691 #ifdef CONFIG_MMC 692 #define CONFIG_FSL_ESDHC 693 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 694 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 695 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 696 #define CONFIG_GENERIC_MMC 697 #define CONFIG_DOS_PARTITION 698 #endif 699 700 /* 701 * Dynamic MTD Partition support with mtdparts 702 */ 703 #ifndef CONFIG_SYS_NO_FLASH 704 #define CONFIG_MTD_DEVICE 705 #define CONFIG_MTD_PARTITIONS 706 #define CONFIG_CMD_MTDPARTS 707 #define CONFIG_FLASH_CFI_MTD 708 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 709 "spi0=spife110000.1" 710 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 711 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 712 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 713 "1m(uboot),5m(kernel),128k(dtb),-(user)" 714 #endif 715 716 /* 717 * Environment 718 */ 719 720 /* 721 * Command line configuration. 722 */ 723 #define CONFIG_CMD_ERRATA 724 #define CONFIG_CMD_REGINFO 725 726 #ifdef CONFIG_PCI 727 #define CONFIG_CMD_PCI 728 #endif 729 730 /* Hash command with SHA acceleration supported in hardware */ 731 #ifdef CONFIG_FSL_CAAM 732 #define CONFIG_CMD_HASH 733 #define CONFIG_SHA_HW_ACCEL 734 #endif 735 736 /* 737 * Miscellaneous configurable options 738 */ 739 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 740 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 741 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 742 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 743 #ifdef CONFIG_CMD_KGDB 744 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 745 #else 746 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 747 #endif 748 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 749 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 750 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 751 752 /* 753 * For booting Linux, the board info and command line data 754 * have to be in the first 64 MB of memory, since this is 755 * the maximum mapped by the Linux kernel during initialization. 756 */ 757 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 758 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 759 760 #ifdef CONFIG_CMD_KGDB 761 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 762 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 763 #endif 764 765 /* 766 * Environment Configuration 767 */ 768 #define CONFIG_ROOTPATH "/opt/nfsroot" 769 #define CONFIG_BOOTFILE "uImage" 770 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 771 772 /* default location for tftp and bootm */ 773 #define CONFIG_LOADADDR 1000000 774 #define CONFIG_BAUDRATE 115200 775 #define __USB_PHY_TYPE utmi 776 777 #define CONFIG_EXTRA_ENV_SETTINGS \ 778 "hwconfig=fsl_ddr:" \ 779 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 780 "bank_intlv=auto;" \ 781 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 782 "netdev=eth0\0" \ 783 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 784 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 785 "tftpflash=tftpboot $loadaddr $uboot && " \ 786 "protect off $ubootaddr +$filesize && " \ 787 "erase $ubootaddr +$filesize && " \ 788 "cp.b $loadaddr $ubootaddr $filesize && " \ 789 "protect on $ubootaddr +$filesize && " \ 790 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 791 "consoledev=ttyS0\0" \ 792 "ramdiskaddr=2000000\0" \ 793 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 794 "fdtaddr=1e00000\0" \ 795 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 796 "bdev=sda3\0" 797 798 /* 799 * For emulation this causes u-boot to jump to the start of the 800 * proof point app code automatically 801 */ 802 #define CONFIG_PROOF_POINTS \ 803 "setenv bootargs root=/dev/$bdev rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "cpu 1 release 0x29000000 - - -;" \ 806 "cpu 2 release 0x29000000 - - -;" \ 807 "cpu 3 release 0x29000000 - - -;" \ 808 "cpu 4 release 0x29000000 - - -;" \ 809 "cpu 5 release 0x29000000 - - -;" \ 810 "cpu 6 release 0x29000000 - - -;" \ 811 "cpu 7 release 0x29000000 - - -;" \ 812 "go 0x29000000" 813 814 #define CONFIG_HVBOOT \ 815 "setenv bootargs config-addr=0x60000000; " \ 816 "bootm 0x01000000 - 0x00f00000" 817 818 #define CONFIG_ALU \ 819 "setenv bootargs root=/dev/$bdev rw " \ 820 "console=$consoledev,$baudrate $othbootargs;" \ 821 "cpu 1 release 0x01000000 - - -;" \ 822 "cpu 2 release 0x01000000 - - -;" \ 823 "cpu 3 release 0x01000000 - - -;" \ 824 "cpu 4 release 0x01000000 - - -;" \ 825 "cpu 5 release 0x01000000 - - -;" \ 826 "cpu 6 release 0x01000000 - - -;" \ 827 "cpu 7 release 0x01000000 - - -;" \ 828 "go 0x01000000" 829 830 #define CONFIG_LINUX \ 831 "setenv bootargs root=/dev/ram rw " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "setenv ramdiskaddr 0x02000000;" \ 834 "setenv fdtaddr 0x00c00000;" \ 835 "setenv loadaddr 0x1000000;" \ 836 "bootm $loadaddr $ramdiskaddr $fdtaddr" 837 838 #define CONFIG_HDBOOT \ 839 "setenv bootargs root=/dev/$bdev rw " \ 840 "console=$consoledev,$baudrate $othbootargs;" \ 841 "tftp $loadaddr $bootfile;" \ 842 "tftp $fdtaddr $fdtfile;" \ 843 "bootm $loadaddr - $fdtaddr" 844 845 #define CONFIG_NFSBOOTCOMMAND \ 846 "setenv bootargs root=/dev/nfs rw " \ 847 "nfsroot=$serverip:$rootpath " \ 848 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 849 "console=$consoledev,$baudrate $othbootargs;" \ 850 "tftp $loadaddr $bootfile;" \ 851 "tftp $fdtaddr $fdtfile;" \ 852 "bootm $loadaddr - $fdtaddr" 853 854 #define CONFIG_RAMBOOTCOMMAND \ 855 "setenv bootargs root=/dev/ram rw " \ 856 "console=$consoledev,$baudrate $othbootargs;" \ 857 "tftp $ramdiskaddr $ramdiskfile;" \ 858 "tftp $loadaddr $bootfile;" \ 859 "tftp $fdtaddr $fdtfile;" \ 860 "bootm $loadaddr $ramdiskaddr $fdtaddr" 861 862 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 863 864 #include <asm/fsl_secure_boot.h> 865 866 #endif /* __T2080RDB_H */ 867