1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 30 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_ENABLE_36BIT_PHYS 35 36 #ifdef CONFIG_PHYS_64BIT 37 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 50 #if defined(CONFIG_PPC_T2080) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 52 #elif defined(CONFIG_PPC_T2081) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 54 #endif 55 56 #define CONFIG_SPL_FLUSH_IMAGE 57 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 58 #define CONFIG_FSL_LAW /* Use common FSL init code */ 59 #define CONFIG_SYS_TEXT_BASE 0x00201000 60 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 61 #define CONFIG_SPL_PAD_TO 0x40000 62 #define CONFIG_SPL_MAX_SIZE 0x28000 63 #define RESET_VECTOR_OFFSET 0x27FFC 64 #define BOOT_PAGE_OFFSET 0x27000 65 #ifdef CONFIG_SPL_BUILD 66 #define CONFIG_SPL_SKIP_RELOCATE 67 #define CONFIG_SPL_COMMON_INIT_DDR 68 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 69 #define CONFIG_SYS_NO_FLASH 70 #endif 71 72 #ifdef CONFIG_NAND 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 75 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 78 #define CONFIG_SPL_NAND_BOOT 79 #endif 80 81 #ifdef CONFIG_SPIFLASH 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 83 #define CONFIG_SPL_SPI_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_SUPPORT 85 #define CONFIG_SPL_SPI_FLASH_MINIMAL 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #define CONFIG_SPL_SPI_BOOT 95 #endif 96 97 #ifdef CONFIG_SDCARD 98 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 99 #define CONFIG_SPL_MMC_MINIMAL 100 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 101 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 102 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 103 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 105 #ifndef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #endif 108 #define CONFIG_SPL_MMC_BOOT 109 #endif 110 111 #endif /* CONFIG_RAMBOOT_PBL */ 112 113 #define CONFIG_SRIO_PCIE_BOOT_MASTER 114 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 115 /* Set 1M boot space */ 116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 117 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 118 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 119 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 120 #define CONFIG_SYS_NO_FLASH 121 #endif 122 123 #ifndef CONFIG_SYS_TEXT_BASE 124 #define CONFIG_SYS_TEXT_BASE 0xeff40000 125 #endif 126 127 #ifndef CONFIG_RESET_VECTOR_ADDRESS 128 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 129 #endif 130 131 /* 132 * These can be toggled for performance analysis, otherwise use default. 133 */ 134 #define CONFIG_SYS_CACHE_STASHING 135 #define CONFIG_BTB /* toggle branch predition */ 136 #define CONFIG_DDR_ECC 137 #ifdef CONFIG_DDR_ECC 138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 139 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 140 #endif 141 142 #ifndef CONFIG_SYS_NO_FLASH 143 #define CONFIG_FLASH_CFI_DRIVER 144 #define CONFIG_SYS_FLASH_CFI 145 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 146 #endif 147 148 #if defined(CONFIG_SPIFLASH) 149 #define CONFIG_SYS_EXTRA_ENV_RELOC 150 #define CONFIG_ENV_IS_IN_SPI_FLASH 151 #define CONFIG_ENV_SPI_BUS 0 152 #define CONFIG_ENV_SPI_CS 0 153 #define CONFIG_ENV_SPI_MAX_HZ 10000000 154 #define CONFIG_ENV_SPI_MODE 0 155 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 156 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 157 #define CONFIG_ENV_SECT_SIZE 0x10000 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_MMC 161 #define CONFIG_SYS_MMC_ENV_DEV 0 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (512 * 0x800) 164 #elif defined(CONFIG_NAND) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_NAND 167 #define CONFIG_ENV_SIZE 0x2000 168 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 169 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 170 #define CONFIG_ENV_IS_IN_REMOTE 171 #define CONFIG_ENV_ADDR 0xffe20000 172 #define CONFIG_ENV_SIZE 0x2000 173 #elif defined(CONFIG_ENV_IS_NOWHERE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #else 176 #define CONFIG_ENV_IS_IN_FLASH 177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 180 #endif 181 182 #ifndef __ASSEMBLY__ 183 unsigned long get_board_sys_clk(void); 184 unsigned long get_board_ddr_clk(void); 185 #endif 186 187 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 188 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 189 190 /* 191 * Config the L3 Cache as L3 SRAM 192 */ 193 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 194 #define CONFIG_SYS_L3_SIZE (512 << 10) 195 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 196 #ifdef CONFIG_RAMBOOT_PBL 197 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 198 #endif 199 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 200 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 201 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 202 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 203 204 #define CONFIG_SYS_DCSRBAR 0xf0000000 205 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 206 207 /* EEPROM */ 208 #define CONFIG_ID_EEPROM 209 #define CONFIG_SYS_I2C_EEPROM_NXID 210 #define CONFIG_SYS_EEPROM_BUS_NUM 0 211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 213 214 /* 215 * DDR Setup 216 */ 217 #define CONFIG_VERY_BIG_RAM 218 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 219 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 220 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 221 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 222 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 223 #define CONFIG_DDR_SPD 224 #define CONFIG_SYS_FSL_DDR3 225 #define CONFIG_FSL_DDR_INTERACTIVE 226 #define CONFIG_SYS_SPD_BUS_NUM 0 227 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 228 #define SPD_EEPROM_ADDRESS1 0x51 229 #define SPD_EEPROM_ADDRESS2 0x52 230 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 231 #define CTRL_INTLV_PREFERED cacheline 232 233 /* 234 * IFC Definitions 235 */ 236 #define CONFIG_SYS_FLASH_BASE 0xe0000000 237 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 238 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 239 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 240 + 0x8000000) | \ 241 CSPR_PORT_SIZE_16 | \ 242 CSPR_MSEL_NOR | \ 243 CSPR_V) 244 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 245 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 246 CSPR_PORT_SIZE_16 | \ 247 CSPR_MSEL_NOR | \ 248 CSPR_V) 249 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 250 /* NOR Flash Timing Params */ 251 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 252 253 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 254 FTIM0_NOR_TEADC(0x5) | \ 255 FTIM0_NOR_TEAHC(0x5)) 256 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 257 FTIM1_NOR_TRAD_NOR(0x1A) |\ 258 FTIM1_NOR_TSEQRAD_NOR(0x13)) 259 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 260 FTIM2_NOR_TCH(0x4) | \ 261 FTIM2_NOR_TWPH(0x0E) | \ 262 FTIM2_NOR_TWP(0x1c)) 263 #define CONFIG_SYS_NOR_FTIM3 0x0 264 265 #define CONFIG_SYS_FLASH_QUIET_TEST 266 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 267 268 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 269 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 270 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 271 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 272 273 #define CONFIG_SYS_FLASH_EMPTY_INFO 274 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 275 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 276 277 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 278 #define QIXIS_BASE 0xffdf0000 279 #define QIXIS_LBMAP_SWITCH 6 280 #define QIXIS_LBMAP_MASK 0x0f 281 #define QIXIS_LBMAP_SHIFT 0 282 #define QIXIS_LBMAP_DFLTBANK 0x00 283 #define QIXIS_LBMAP_ALTBANK 0x04 284 #define QIXIS_LBMAP_NAND 0x09 285 #define QIXIS_LBMAP_SD 0x00 286 #define QIXIS_RCW_SRC_NAND 0x104 287 #define QIXIS_RCW_SRC_SD 0x040 288 #define QIXIS_RST_CTL_RESET 0x83 289 #define QIXIS_RST_FORCE_MEM 0x1 290 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 291 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 292 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 293 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 294 295 #define CONFIG_SYS_CSPR3_EXT (0xf) 296 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 297 | CSPR_PORT_SIZE_8 \ 298 | CSPR_MSEL_GPCM \ 299 | CSPR_V) 300 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 301 #define CONFIG_SYS_CSOR3 0x0 302 /* QIXIS Timing parameters for IFC CS3 */ 303 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 304 FTIM0_GPCM_TEADC(0x0e) | \ 305 FTIM0_GPCM_TEAHC(0x0e)) 306 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 307 FTIM1_GPCM_TRAD(0x3f)) 308 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 309 FTIM2_GPCM_TCH(0x8) | \ 310 FTIM2_GPCM_TWP(0x1f)) 311 #define CONFIG_SYS_CS3_FTIM3 0x0 312 313 /* NAND Flash on IFC */ 314 #define CONFIG_NAND_FSL_IFC 315 #define CONFIG_SYS_NAND_BASE 0xff800000 316 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 317 318 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 319 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 320 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 321 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 322 | CSPR_V) 323 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 324 325 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 326 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 327 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 328 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 329 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 330 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 331 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 332 333 #define CONFIG_SYS_NAND_ONFI_DETECTION 334 335 /* ONFI NAND Flash mode0 Timing Params */ 336 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 337 FTIM0_NAND_TWP(0x18) | \ 338 FTIM0_NAND_TWCHT(0x07) | \ 339 FTIM0_NAND_TWH(0x0a)) 340 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 341 FTIM1_NAND_TWBE(0x39) | \ 342 FTIM1_NAND_TRR(0x0e) | \ 343 FTIM1_NAND_TRP(0x18)) 344 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 345 FTIM2_NAND_TREH(0x0a) | \ 346 FTIM2_NAND_TWHRE(0x1e)) 347 #define CONFIG_SYS_NAND_FTIM3 0x0 348 349 #define CONFIG_SYS_NAND_DDR_LAW 11 350 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 351 #define CONFIG_SYS_MAX_NAND_DEVICE 1 352 #define CONFIG_CMD_NAND 353 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 354 355 #if defined(CONFIG_NAND) 356 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 357 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 358 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 359 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 360 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 361 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 362 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 363 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 364 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 365 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 366 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 367 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 368 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 369 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 370 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 371 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 372 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 373 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 374 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 375 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 376 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 377 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 378 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 379 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 380 #else 381 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 382 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 383 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 384 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 385 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 386 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 387 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 388 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 389 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 390 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 391 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 392 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 393 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 394 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 395 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 396 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 397 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 398 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 399 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 400 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 401 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 402 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 403 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 404 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 405 #endif 406 407 #if defined(CONFIG_RAMBOOT_PBL) 408 #define CONFIG_SYS_RAMBOOT 409 #endif 410 411 #ifdef CONFIG_SPL_BUILD 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 413 #else 414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 415 #endif 416 417 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 418 #define CONFIG_MISC_INIT_R 419 #define CONFIG_HWCONFIG 420 421 /* define to use L1 as initial stack */ 422 #define CONFIG_L1_INIT_RAM 423 #define CONFIG_SYS_INIT_RAM_LOCK 424 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 427 /* The assembler doesn't like typecast */ 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 429 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 430 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 431 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 432 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 433 GENERATED_GBL_DATA_SIZE) 434 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 435 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 436 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 437 438 /* 439 * Serial Port 440 */ 441 #define CONFIG_CONS_INDEX 1 442 #define CONFIG_SYS_NS16550_SERIAL 443 #define CONFIG_SYS_NS16550_REG_SIZE 1 444 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 445 #define CONFIG_SYS_BAUDRATE_TABLE \ 446 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 447 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 448 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 449 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 450 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 451 452 /* 453 * I2C 454 */ 455 #define CONFIG_SYS_I2C 456 #define CONFIG_SYS_I2C_FSL 457 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 458 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 459 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 460 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 461 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 462 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 463 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 464 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 465 #define CONFIG_SYS_FSL_I2C_SPEED 100000 466 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 467 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 468 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 469 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 470 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 471 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 472 #define I2C_MUX_CH_DEFAULT 0x8 473 474 #define I2C_MUX_CH_VOL_MONITOR 0xa 475 476 /* Voltage monitor on channel 2*/ 477 #define I2C_VOL_MONITOR_ADDR 0x40 478 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 479 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 480 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 481 482 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 483 #ifndef CONFIG_SPL_BUILD 484 #define CONFIG_VID 485 #endif 486 #define CONFIG_VOL_MONITOR_IR36021_SET 487 #define CONFIG_VOL_MONITOR_IR36021_READ 488 /* The lowest and highest voltage allowed for T208xQDS */ 489 #define VDD_MV_MIN 819 490 #define VDD_MV_MAX 1212 491 492 /* 493 * RapidIO 494 */ 495 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 496 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 497 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 498 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 499 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 500 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 501 /* 502 * for slave u-boot IMAGE instored in master memory space, 503 * PHYS must be aligned based on the SIZE 504 */ 505 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 506 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 507 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 508 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 509 /* 510 * for slave UCODE and ENV instored in master memory space, 511 * PHYS must be aligned based on the SIZE 512 */ 513 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 514 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 515 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 516 517 /* slave core release by master*/ 518 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 519 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 520 521 /* 522 * SRIO_PCIE_BOOT - SLAVE 523 */ 524 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 525 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 526 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 527 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 528 #endif 529 530 /* 531 * eSPI - Enhanced SPI 532 */ 533 #ifdef CONFIG_SPI_FLASH 534 #ifndef CONFIG_SPL_BUILD 535 #endif 536 537 #define CONFIG_SPI_FLASH_BAR 538 #define CONFIG_SF_DEFAULT_SPEED 10000000 539 #define CONFIG_SF_DEFAULT_MODE 0 540 #endif 541 542 /* 543 * General PCI 544 * Memory space is mapped 1-1, but I/O space must start from 0. 545 */ 546 #define CONFIG_PCI /* Enable PCI/PCIE */ 547 #define CONFIG_PCIE1 /* PCIE controller 1 */ 548 #define CONFIG_PCIE2 /* PCIE controller 2 */ 549 #define CONFIG_PCIE3 /* PCIE controller 3 */ 550 #define CONFIG_PCIE4 /* PCIE controller 4 */ 551 #define CONFIG_FSL_PCIE_RESET 552 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 553 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 554 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 555 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 556 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 558 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 559 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 560 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 561 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 562 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 563 564 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 565 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 566 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 567 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 568 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 569 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 570 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 571 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 572 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 573 574 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 575 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 576 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 577 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 578 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 579 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 580 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 581 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 582 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 583 584 /* controller 4, Base address 203000 */ 585 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 586 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 587 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 588 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 589 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 590 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 591 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 592 593 #ifdef CONFIG_PCI 594 #define CONFIG_PCI_INDIRECT_BRIDGE 595 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 596 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 597 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 598 #define CONFIG_DOS_PARTITION 599 #endif 600 601 /* Qman/Bman */ 602 #ifndef CONFIG_NOBQFMAN 603 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 604 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 605 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 606 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 607 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 608 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 609 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 610 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 611 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 612 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 613 CONFIG_SYS_BMAN_CENA_SIZE) 614 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 615 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 616 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 617 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 618 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 619 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 620 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 621 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 622 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 623 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 624 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 625 CONFIG_SYS_QMAN_CENA_SIZE) 626 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 627 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 628 629 #define CONFIG_SYS_DPAA_FMAN 630 #define CONFIG_SYS_DPAA_PME 631 #define CONFIG_SYS_PMAN 632 #define CONFIG_SYS_DPAA_DCE 633 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 634 #define CONFIG_SYS_INTERLAKEN 635 636 /* Default address of microcode for the Linux Fman driver */ 637 #if defined(CONFIG_SPIFLASH) 638 /* 639 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 640 * env, so we got 0x110000. 641 */ 642 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 643 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 644 #elif defined(CONFIG_SDCARD) 645 /* 646 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 647 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 648 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 649 */ 650 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 651 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 652 #elif defined(CONFIG_NAND) 653 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 654 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 655 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 656 /* 657 * Slave has no ucode locally, it can fetch this from remote. When implementing 658 * in two corenet boards, slave's ucode could be stored in master's memory 659 * space, the address can be mapped from slave TLB->slave LAW-> 660 * slave SRIO or PCIE outbound window->master inbound window-> 661 * master LAW->the ucode address in master's memory space. 662 */ 663 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 664 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 665 #else 666 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 667 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 668 #endif 669 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 670 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 671 #endif /* CONFIG_NOBQFMAN */ 672 673 #ifdef CONFIG_SYS_DPAA_FMAN 674 #define CONFIG_FMAN_ENET 675 #define CONFIG_PHYLIB_10G 676 #define CONFIG_PHY_VITESSE 677 #define CONFIG_PHY_REALTEK 678 #define CONFIG_PHY_TERANETICS 679 #define RGMII_PHY1_ADDR 0x1 680 #define RGMII_PHY2_ADDR 0x2 681 #define FM1_10GEC1_PHY_ADDR 0x3 682 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 683 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 684 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 685 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 686 #endif 687 688 #ifdef CONFIG_FMAN_ENET 689 #define CONFIG_MII /* MII PHY management */ 690 #define CONFIG_ETHPRIME "FM1@DTSEC3" 691 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 692 #endif 693 694 /* 695 * SATA 696 */ 697 #ifdef CONFIG_FSL_SATA_V2 698 #define CONFIG_LIBATA 699 #define CONFIG_FSL_SATA 700 #define CONFIG_SYS_SATA_MAX_DEVICE 2 701 #define CONFIG_SATA1 702 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 703 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 704 #define CONFIG_SATA2 705 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 706 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 707 #define CONFIG_LBA48 708 #define CONFIG_CMD_SATA 709 #define CONFIG_DOS_PARTITION 710 #endif 711 712 /* 713 * USB 714 */ 715 #ifdef CONFIG_USB_EHCI 716 #define CONFIG_USB_EHCI_FSL 717 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 718 #define CONFIG_HAS_FSL_DR_USB 719 #endif 720 721 /* 722 * SDHC 723 */ 724 #ifdef CONFIG_MMC 725 #define CONFIG_FSL_ESDHC 726 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 727 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 728 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 729 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 730 #define CONFIG_GENERIC_MMC 731 #define CONFIG_DOS_PARTITION 732 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 733 #endif 734 735 /* 736 * Dynamic MTD Partition support with mtdparts 737 */ 738 #ifndef CONFIG_SYS_NO_FLASH 739 #define CONFIG_MTD_DEVICE 740 #define CONFIG_MTD_PARTITIONS 741 #define CONFIG_CMD_MTDPARTS 742 #define CONFIG_FLASH_CFI_MTD 743 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 744 "spi0=spife110000.0" 745 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 746 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 747 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 748 "1m(uboot),5m(kernel),128k(dtb),-(user)" 749 #endif 750 751 /* 752 * Environment 753 */ 754 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 755 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 756 757 /* 758 * Command line configuration. 759 */ 760 #define CONFIG_CMD_ERRATA 761 #define CONFIG_CMD_IRQ 762 #define CONFIG_CMD_REGINFO 763 764 #ifdef CONFIG_PCI 765 #define CONFIG_CMD_PCI 766 #endif 767 768 /* Hash command with SHA acceleration supported in hardware */ 769 #ifdef CONFIG_FSL_CAAM 770 #define CONFIG_CMD_HASH 771 #define CONFIG_SHA_HW_ACCEL 772 #endif 773 774 /* 775 * Miscellaneous configurable options 776 */ 777 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 778 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 779 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 780 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 781 #ifdef CONFIG_CMD_KGDB 782 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 783 #else 784 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 785 #endif 786 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 787 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 788 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 789 790 /* 791 * For booting Linux, the board info and command line data 792 * have to be in the first 64 MB of memory, since this is 793 * the maximum mapped by the Linux kernel during initialization. 794 */ 795 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 796 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 797 798 #ifdef CONFIG_CMD_KGDB 799 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 800 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 801 #endif 802 803 /* 804 * Environment Configuration 805 */ 806 #define CONFIG_ROOTPATH "/opt/nfsroot" 807 #define CONFIG_BOOTFILE "uImage" 808 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 809 810 /* default location for tftp and bootm */ 811 #define CONFIG_LOADADDR 1000000 812 #define CONFIG_BAUDRATE 115200 813 #define __USB_PHY_TYPE utmi 814 815 #define CONFIG_EXTRA_ENV_SETTINGS \ 816 "hwconfig=fsl_ddr:" \ 817 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 818 "bank_intlv=auto;" \ 819 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 820 "netdev=eth0\0" \ 821 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 822 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 823 "tftpflash=tftpboot $loadaddr $uboot && " \ 824 "protect off $ubootaddr +$filesize && " \ 825 "erase $ubootaddr +$filesize && " \ 826 "cp.b $loadaddr $ubootaddr $filesize && " \ 827 "protect on $ubootaddr +$filesize && " \ 828 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 829 "consoledev=ttyS0\0" \ 830 "ramdiskaddr=2000000\0" \ 831 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 832 "fdtaddr=1e00000\0" \ 833 "fdtfile=t2080qds/t2080qds.dtb\0" \ 834 "bdev=sda3\0" 835 836 /* 837 * For emulation this causes u-boot to jump to the start of the 838 * proof point app code automatically 839 */ 840 #define CONFIG_PROOF_POINTS \ 841 "setenv bootargs root=/dev/$bdev rw " \ 842 "console=$consoledev,$baudrate $othbootargs;" \ 843 "cpu 1 release 0x29000000 - - -;" \ 844 "cpu 2 release 0x29000000 - - -;" \ 845 "cpu 3 release 0x29000000 - - -;" \ 846 "cpu 4 release 0x29000000 - - -;" \ 847 "cpu 5 release 0x29000000 - - -;" \ 848 "cpu 6 release 0x29000000 - - -;" \ 849 "cpu 7 release 0x29000000 - - -;" \ 850 "go 0x29000000" 851 852 #define CONFIG_HVBOOT \ 853 "setenv bootargs config-addr=0x60000000; " \ 854 "bootm 0x01000000 - 0x00f00000" 855 856 #define CONFIG_ALU \ 857 "setenv bootargs root=/dev/$bdev rw " \ 858 "console=$consoledev,$baudrate $othbootargs;" \ 859 "cpu 1 release 0x01000000 - - -;" \ 860 "cpu 2 release 0x01000000 - - -;" \ 861 "cpu 3 release 0x01000000 - - -;" \ 862 "cpu 4 release 0x01000000 - - -;" \ 863 "cpu 5 release 0x01000000 - - -;" \ 864 "cpu 6 release 0x01000000 - - -;" \ 865 "cpu 7 release 0x01000000 - - -;" \ 866 "go 0x01000000" 867 868 #define CONFIG_LINUX \ 869 "setenv bootargs root=/dev/ram rw " \ 870 "console=$consoledev,$baudrate $othbootargs;" \ 871 "setenv ramdiskaddr 0x02000000;" \ 872 "setenv fdtaddr 0x00c00000;" \ 873 "setenv loadaddr 0x1000000;" \ 874 "bootm $loadaddr $ramdiskaddr $fdtaddr" 875 876 #define CONFIG_HDBOOT \ 877 "setenv bootargs root=/dev/$bdev rw " \ 878 "console=$consoledev,$baudrate $othbootargs;" \ 879 "tftp $loadaddr $bootfile;" \ 880 "tftp $fdtaddr $fdtfile;" \ 881 "bootm $loadaddr - $fdtaddr" 882 883 #define CONFIG_NFSBOOTCOMMAND \ 884 "setenv bootargs root=/dev/nfs rw " \ 885 "nfsroot=$serverip:$rootpath " \ 886 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 887 "console=$consoledev,$baudrate $othbootargs;" \ 888 "tftp $loadaddr $bootfile;" \ 889 "tftp $fdtaddr $fdtfile;" \ 890 "bootm $loadaddr - $fdtaddr" 891 892 #define CONFIG_RAMBOOTCOMMAND \ 893 "setenv bootargs root=/dev/ram rw " \ 894 "console=$consoledev,$baudrate $othbootargs;" \ 895 "tftp $ramdiskaddr $ramdiskfile;" \ 896 "tftp $loadaddr $bootfile;" \ 897 "tftp $fdtaddr $fdtfile;" \ 898 "bootm $loadaddr $ramdiskaddr $fdtaddr" 899 900 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 901 902 #include <asm/fsl_secure_boot.h> 903 904 #endif /* __T208xQDS_H */ 905