1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_MP 1 /* support multiple processors */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ 42 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 43 44 /* 45 * default CCSRBAR is at 0xff700000 46 * assume U-Boot is less than 0.5MB 47 */ 48 #define CONFIG_SYS_TEXT_BASE 0xeff00000 49 50 #ifdef RUN_DIAG 51 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 52 #endif 53 54 /* 55 * virtual address to be used for temporary mappings. There 56 * should be 128k free at this VA. 57 */ 58 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 59 60 #define CONFIG_SYS_SRIO 61 #define CONFIG_SRIO1 /* SRIO port 1 */ 62 63 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 64 #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ 65 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ 66 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 67 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 68 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 69 70 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 71 #define CONFIG_ENV_OVERWRITE 72 73 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 74 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 75 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 76 77 #define CONFIG_ALTIVEC 1 78 79 /* 80 * L2CR setup -- make sure this is right for your board! 81 */ 82 #define CONFIG_SYS_L2 83 #define L2_INIT 0 84 #define L2_ENABLE (L2CR_L2E) 85 86 #ifndef CONFIG_SYS_CLK_FREQ 87 #ifndef __ASSEMBLY__ 88 extern unsigned long get_board_sys_clk(unsigned long dummy); 89 #endif 90 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 91 #endif 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 95 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 96 #define CONFIG_SYS_MEMTEST_END 0x00400000 97 98 /* 99 * With the exception of PCI Memory and Rapid IO, most devices will simply 100 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 101 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 102 */ 103 #ifdef CONFIG_PHYS_64BIT 104 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL 105 #else 106 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 107 #endif 108 109 /* 110 * Base addresses -- Note these are effective addresses where the 111 * actual resources get mapped (not physical addresses) 112 */ 113 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 114 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 115 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 116 117 /* Physical addresses */ 118 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 119 #ifdef CONFIG_PHYS_64BIT 120 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 121 #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 122 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) 123 #else 124 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 125 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 126 #endif 127 128 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 129 130 /* 131 * DDR Setup 132 */ 133 #define CONFIG_FSL_DDR2 134 #undef CONFIG_FSL_DDR_INTERACTIVE 135 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 136 #define CONFIG_DDR_SPD 137 138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 139 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 140 141 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 142 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 143 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 144 #define CONFIG_VERY_BIG_RAM 145 146 #define CONFIG_NUM_DDR_CONTROLLERS 2 147 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 148 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 149 150 /* 151 * I2C addresses of SPD EEPROMs 152 */ 153 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 154 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 155 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 156 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 157 158 159 /* 160 * These are used when DDR doesn't use SPD. 161 */ 162 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 163 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 164 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 165 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 166 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 167 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 168 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 169 #define CONFIG_SYS_DDR_MODE_1 0x00480432 170 #define CONFIG_SYS_DDR_MODE_2 0x00000000 171 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 172 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 173 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 174 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 175 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 176 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 177 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 178 179 #define CONFIG_ID_EEPROM 180 #define CONFIG_SYS_I2C_EEPROM_NXID 181 #define CONFIG_ID_EEPROM 182 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 184 185 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 186 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ 187 | CONFIG_SYS_PHYS_ADDR_HIGH) 188 189 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 190 191 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 192 | 0x00001001) /* port size 16bit */ 193 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 194 195 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 196 | 0x00001001) /* port size 16bit */ 197 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 198 199 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 200 | 0x00000801) /* port size 8bit */ 201 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 202 203 /* 204 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 205 * The PIXIS and CF by themselves aren't large enough to take up the 128k 206 * required for the smallest BAT mapping, so there's a 64k hole. 207 */ 208 #define CONFIG_SYS_LBC_BASE 0xffde0000 209 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ 210 | CONFIG_SYS_PHYS_ADDR_HIGH) 211 212 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 213 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 214 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) 215 #define PIXIS_SIZE 0x00008000 /* 32k */ 216 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 217 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 218 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 219 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 220 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 221 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 222 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 223 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 224 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 225 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 226 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 227 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 228 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 229 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 230 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 231 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 232 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 233 234 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 235 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 236 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 237 238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 239 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 240 241 #undef CONFIG_SYS_FLASH_CHECKSUM 242 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 243 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 244 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 245 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 246 247 #define CONFIG_FLASH_CFI_DRIVER 248 #define CONFIG_SYS_FLASH_CFI 249 #define CONFIG_SYS_FLASH_EMPTY_INFO 250 251 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 252 #define CONFIG_SYS_RAMBOOT 253 #else 254 #undef CONFIG_SYS_RAMBOOT 255 #endif 256 257 #if defined(CONFIG_SYS_RAMBOOT) 258 #undef CONFIG_SPD_EEPROM 259 #define CONFIG_SYS_SDRAM_SIZE 256 260 #endif 261 262 #undef CONFIG_CLOCKS_IN_MHZ 263 264 #define CONFIG_SYS_INIT_RAM_LOCK 1 265 #ifndef CONFIG_SYS_INIT_RAM_LOCK 266 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 267 #else 268 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 269 #endif 270 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 271 272 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 273 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 274 275 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 276 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 277 278 /* Serial Port */ 279 #define CONFIG_CONS_INDEX 1 280 #define CONFIG_SYS_NS16550 281 #define CONFIG_SYS_NS16550_SERIAL 282 #define CONFIG_SYS_NS16550_REG_SIZE 1 283 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 284 285 #define CONFIG_SYS_BAUDRATE_TABLE \ 286 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 287 288 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 289 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 290 291 /* Use the HUSH parser */ 292 #define CONFIG_SYS_HUSH_PARSER 293 #ifdef CONFIG_SYS_HUSH_PARSER 294 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 295 #endif 296 297 /* 298 * Pass open firmware flat tree to kernel 299 */ 300 #define CONFIG_OF_LIBFDT 1 301 #define CONFIG_OF_BOARD_SETUP 1 302 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 303 304 /* 305 * I2C 306 */ 307 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 308 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 309 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 310 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 311 #define CONFIG_SYS_I2C_SLAVE 0x7F 312 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 313 #define CONFIG_SYS_I2C_OFFSET 0x3100 314 315 /* 316 * RapidIO MMU 317 */ 318 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 319 #ifdef CONFIG_PHYS_64BIT 320 #define CONFIG_SYS_SRIO1_MEM_PHYS 0x0000000c00000000ULL 321 #else 322 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE 323 #endif 324 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 325 326 /* 327 * General PCI 328 * Addresses are mapped 1-1. 329 */ 330 331 #define CONFIG_SYS_PCIE1_NAME "ULI" 332 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 333 #ifdef CONFIG_PHYS_64BIT 334 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 335 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL 336 #else 337 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 338 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT 339 #endif 340 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 341 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 342 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 343 #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ 344 | CONFIG_SYS_PHYS_ADDR_HIGH) 345 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 346 347 #ifdef CONFIG_PHYS_64BIT 348 /* 349 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 350 * This will increase the amount of PCI address space available for 351 * for mapping RAM. 352 */ 353 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 354 #else 355 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 356 + CONFIG_SYS_PCIE1_MEM_SIZE) 357 #endif 358 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 359 + CONFIG_SYS_PCIE1_MEM_SIZE) 360 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 361 + CONFIG_SYS_PCIE1_MEM_SIZE) 362 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 363 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 364 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 365 + CONFIG_SYS_PCIE1_IO_SIZE) 366 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 367 + CONFIG_SYS_PCIE1_IO_SIZE) 368 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 369 370 #if defined(CONFIG_PCI) 371 372 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 373 374 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 375 376 #define CONFIG_NET_MULTI 377 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 378 379 #define CONFIG_RTL8139 380 381 #undef CONFIG_EEPRO100 382 #undef CONFIG_TULIP 383 384 /************************************************************ 385 * USB support 386 ************************************************************/ 387 #define CONFIG_PCI_OHCI 1 388 #define CONFIG_USB_OHCI_NEW 1 389 #define CONFIG_USB_KEYBOARD 1 390 #define CONFIG_SYS_STDIO_DEREGISTER 391 #define CONFIG_SYS_USB_EVENT_POLL 1 392 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 393 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 394 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 395 396 /*PCIE video card used*/ 397 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 398 399 /*PCI video card used*/ 400 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 401 402 /* video */ 403 #define CONFIG_VIDEO 404 405 #if defined(CONFIG_VIDEO) 406 #define CONFIG_BIOSEMU 407 #define CONFIG_CFB_CONSOLE 408 #define CONFIG_VIDEO_SW_CURSOR 409 #define CONFIG_VGA_AS_SINGLE_DEVICE 410 #define CONFIG_ATI_RADEON_FB 411 #define CONFIG_VIDEO_LOGO 412 /*#define CONFIG_CONSOLE_CURSOR*/ 413 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 414 #endif 415 416 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 417 418 #define CONFIG_DOS_PARTITION 419 #define CONFIG_SCSI_AHCI 420 421 #ifdef CONFIG_SCSI_AHCI 422 #define CONFIG_SATA_ULI5288 423 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 424 #define CONFIG_SYS_SCSI_MAX_LUN 1 425 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 426 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 427 #endif 428 429 #endif /* CONFIG_PCI */ 430 431 #if defined(CONFIG_TSEC_ENET) 432 433 #ifndef CONFIG_NET_MULTI 434 #define CONFIG_NET_MULTI 1 435 #endif 436 437 #define CONFIG_MII 1 /* MII PHY management */ 438 439 #define CONFIG_TSEC1 1 440 #define CONFIG_TSEC1_NAME "eTSEC1" 441 #define CONFIG_TSEC2 1 442 #define CONFIG_TSEC2_NAME "eTSEC2" 443 #define CONFIG_TSEC3 1 444 #define CONFIG_TSEC3_NAME "eTSEC3" 445 #define CONFIG_TSEC4 1 446 #define CONFIG_TSEC4_NAME "eTSEC4" 447 448 #define TSEC1_PHY_ADDR 0 449 #define TSEC2_PHY_ADDR 1 450 #define TSEC3_PHY_ADDR 2 451 #define TSEC4_PHY_ADDR 3 452 #define TSEC1_PHYIDX 0 453 #define TSEC2_PHYIDX 0 454 #define TSEC3_PHYIDX 0 455 #define TSEC4_PHYIDX 0 456 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 457 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 458 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 459 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 460 461 #define CONFIG_ETHPRIME "eTSEC1" 462 463 #endif /* CONFIG_TSEC_ENET */ 464 465 /* Contort an addr into the format needed for BATs */ 466 #ifdef CONFIG_PHYS_64BIT 467 #define BAT_PHYS_ADDR(x) ((unsigned long) \ 468 ((x & 0x00000000ffffffffULL) | \ 469 ((x & 0x0000000e00000000ULL) >> 24) | \ 470 ((x & 0x0000000100000000ULL) >> 30))) 471 #else 472 #define BAT_PHYS_ADDR(x) (x) 473 #endif 474 475 476 /* Put high physical address bits into the BAT format */ 477 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 478 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 479 480 /* 481 * BAT0 DDR 482 */ 483 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 484 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 485 486 /* 487 * BAT1 LBC (PIXIS/CF) 488 */ 489 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 490 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 491 BATL_GUARDEDSTORAGE) 492 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 493 | BATU_VS | BATU_VP) 494 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 495 | BATL_PP_RW | BATL_MEMCOHERENCE) 496 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 497 498 /* if CONFIG_PCI: 499 * BAT2 PCIE1 and PCIE1 MEM 500 * if CONFIG_RIO 501 * BAT2 Rapidio Memory 502 */ 503 #ifdef CONFIG_PCI 504 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ 505 | BATL_PP_RW | BATL_CACHEINHIBIT \ 506 | BATL_GUARDEDSTORAGE) 507 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 508 | BATU_VS | BATU_VP) 509 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ 510 | BATL_PP_RW | BATL_CACHEINHIBIT) 511 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 512 #else /* CONFIG_RIO */ 513 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ 514 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 515 BATL_GUARDEDSTORAGE) 516 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 517 | BATU_VS | BATU_VP) 518 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ 519 | BATL_PP_RW | BATL_CACHEINHIBIT) 520 521 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \ 522 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 523 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 524 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 525 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 526 #endif 527 528 /* 529 * BAT3 CCSR Space 530 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs 531 * instead. The assembler chokes on ULL. 532 */ 533 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 534 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 535 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 536 | BATL_PP_RW | BATL_CACHEINHIBIT \ 537 | BATL_GUARDEDSTORAGE) 538 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 539 | BATU_VP) 540 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 541 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 542 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 543 | BATL_PP_RW | BATL_CACHEINHIBIT) 544 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 545 546 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 547 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 548 | BATL_PP_RW | BATL_CACHEINHIBIT \ 549 | BATL_GUARDEDSTORAGE) 550 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 551 | BATU_BL_1M | BATU_VS | BATU_VP) 552 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 553 | BATL_PP_RW | BATL_CACHEINHIBIT) 554 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 555 #endif 556 557 /* 558 * BAT4 PCIE1_IO and PCIE2_IO 559 */ 560 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ 561 | BATL_PP_RW | BATL_CACHEINHIBIT \ 562 | BATL_GUARDEDSTORAGE) 563 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 564 | BATU_VS | BATU_VP) 565 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ 566 | BATL_PP_RW | BATL_CACHEINHIBIT) 567 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 568 569 /* 570 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 571 */ 572 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 573 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 574 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 575 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 576 577 /* 578 * BAT6 FLASH 579 */ 580 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 581 | BATL_PP_RW | BATL_CACHEINHIBIT \ 582 | BATL_GUARDEDSTORAGE) 583 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 584 | BATU_VP) 585 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 586 | BATL_PP_RW | BATL_MEMCOHERENCE) 587 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 588 589 /* Map the last 1M of flash where we're running from reset */ 590 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 591 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 592 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 593 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 594 | BATL_MEMCOHERENCE) 595 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 596 597 /* 598 * BAT7 FREE - used later for tmp mappings 599 */ 600 #define CONFIG_SYS_DBAT7L 0x00000000 601 #define CONFIG_SYS_DBAT7U 0x00000000 602 #define CONFIG_SYS_IBAT7L 0x00000000 603 #define CONFIG_SYS_IBAT7U 0x00000000 604 605 /* 606 * Environment 607 */ 608 #ifndef CONFIG_SYS_RAMBOOT 609 #define CONFIG_ENV_IS_IN_FLASH 1 610 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 611 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 612 #else 613 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 614 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 615 #endif 616 #define CONFIG_ENV_SIZE 0x2000 617 618 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 619 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 620 621 622 /* 623 * BOOTP options 624 */ 625 #define CONFIG_BOOTP_BOOTFILESIZE 626 #define CONFIG_BOOTP_BOOTPATH 627 #define CONFIG_BOOTP_GATEWAY 628 #define CONFIG_BOOTP_HOSTNAME 629 630 631 /* 632 * Command line configuration. 633 */ 634 #include <config_cmd_default.h> 635 636 #define CONFIG_CMD_PING 637 #define CONFIG_CMD_I2C 638 #define CONFIG_CMD_REGINFO 639 640 #if defined(CONFIG_SYS_RAMBOOT) 641 #undef CONFIG_CMD_SAVEENV 642 #endif 643 644 #if defined(CONFIG_PCI) 645 #define CONFIG_CMD_PCI 646 #define CONFIG_CMD_SCSI 647 #define CONFIG_CMD_EXT2 648 #define CONFIG_CMD_USB 649 #endif 650 651 652 #undef CONFIG_WATCHDOG /* watchdog disabled */ 653 654 /* 655 * Miscellaneous configurable options 656 */ 657 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 658 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 659 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 660 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 661 662 #if defined(CONFIG_CMD_KGDB) 663 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 664 #else 665 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 666 #endif 667 668 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 669 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 670 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 671 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 672 673 /* 674 * For booting Linux, the board info and command line data 675 * have to be in the first 8 MB of memory, since this is 676 * the maximum mapped by the Linux kernel during initialization. 677 */ 678 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 679 680 #if defined(CONFIG_CMD_KGDB) 681 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 682 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 683 #endif 684 685 /* 686 * Environment Configuration 687 */ 688 689 /* The mac addresses for all ethernet interface */ 690 #if defined(CONFIG_TSEC_ENET) 691 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 692 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 693 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 694 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 695 #endif 696 697 #define CONFIG_HAS_ETH0 1 698 #define CONFIG_HAS_ETH1 1 699 #define CONFIG_HAS_ETH2 1 700 #define CONFIG_HAS_ETH3 1 701 702 #define CONFIG_IPADDR 192.168.1.100 703 704 #define CONFIG_HOSTNAME unknown 705 #define CONFIG_ROOTPATH /opt/nfsroot 706 #define CONFIG_BOOTFILE uImage 707 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 708 709 #define CONFIG_SERVERIP 192.168.1.1 710 #define CONFIG_GATEWAYIP 192.168.1.1 711 #define CONFIG_NETMASK 255.255.255.0 712 713 /* default location for tftp and bootm */ 714 #define CONFIG_LOADADDR 1000000 715 716 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 717 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 718 719 #define CONFIG_BAUDRATE 115200 720 721 #define CONFIG_EXTRA_ENV_SETTINGS \ 722 "netdev=eth0\0" \ 723 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 724 "tftpflash=tftpboot $loadaddr $uboot; " \ 725 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 726 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 727 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 728 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 729 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 730 "consoledev=ttyS0\0" \ 731 "ramdiskaddr=2000000\0" \ 732 "ramdiskfile=your.ramdisk.u-boot\0" \ 733 "fdtaddr=c00000\0" \ 734 "fdtfile=mpc8641_hpcn.dtb\0" \ 735 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 736 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 737 "maxcpus=2" 738 739 740 #define CONFIG_NFSBOOTCOMMAND \ 741 "setenv bootargs root=/dev/nfs rw " \ 742 "nfsroot=$serverip:$rootpath " \ 743 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 744 "console=$consoledev,$baudrate $othbootargs;" \ 745 "tftp $loadaddr $bootfile;" \ 746 "tftp $fdtaddr $fdtfile;" \ 747 "bootm $loadaddr - $fdtaddr" 748 749 #define CONFIG_RAMBOOTCOMMAND \ 750 "setenv bootargs root=/dev/ram rw " \ 751 "console=$consoledev,$baudrate $othbootargs;" \ 752 "tftp $ramdiskaddr $ramdiskfile;" \ 753 "tftp $loadaddr $bootfile;" \ 754 "tftp $fdtaddr $fdtfile;" \ 755 "bootm $loadaddr $ramdiskaddr $fdtaddr" 756 757 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 758 759 #endif /* __CONFIG_H */ 760