1 /* 2 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8572ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #include "../board/freescale/common/ics307_clk.h" 31 32 #ifdef CONFIG_36BIT 33 #define CONFIG_PHYS_64BIT 34 #endif 35 36 #ifdef CONFIG_NAND 37 #define CONFIG_NAND_U_BOOT 38 #define CONFIG_RAMBOOT_NAND 39 #ifdef CONFIG_NAND_SPL 40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 42 #else 43 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 44 #endif /* CONFIG_NAND_SPL */ 45 #endif 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff80000 49 #endif 50 51 #ifndef CONFIG_SYS_MONITOR_BASE 52 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 53 #endif 54 55 /* High Level Configuration Options */ 56 #define CONFIG_BOOKE 1 /* BOOKE */ 57 #define CONFIG_E500 1 /* BOOKE e500 family */ 58 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 59 #define CONFIG_MPC8572 1 60 #define CONFIG_MPC8572DS 1 61 #define CONFIG_MP 1 /* support multiple processors */ 62 63 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 64 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 65 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 66 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 67 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 68 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 69 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 70 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 71 72 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 73 74 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 75 #define CONFIG_ENV_OVERWRITE 76 77 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 78 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 79 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 80 81 /* 82 * These can be toggled for performance analysis, otherwise use default. 83 */ 84 #define CONFIG_L2_CACHE /* toggle L2 cache */ 85 #define CONFIG_BTB /* toggle branch predition */ 86 87 #define CONFIG_ENABLE_36BIT_PHYS 1 88 89 #ifdef CONFIG_PHYS_64BIT 90 #define CONFIG_ADDR_MAP 1 91 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 92 #endif 93 94 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 95 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 96 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 97 98 /* 99 * Config the L2 Cache as L2 SRAM 100 */ 101 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 102 #ifdef CONFIG_PHYS_64BIT 103 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 104 #else 105 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 106 #endif 107 #define CONFIG_SYS_L2_SIZE (512 << 10) 108 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 109 110 /* 111 * Base addresses -- Note these are effective addresses where the 112 * actual resources get mapped (not physical addresses) 113 */ 114 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 117 #else 118 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 119 #endif 120 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 121 122 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 123 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 124 #else 125 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 126 #endif 127 128 /* DDR Setup */ 129 #define CONFIG_VERY_BIG_RAM 130 #define CONFIG_FSL_DDR2 131 #undef CONFIG_FSL_DDR_INTERACTIVE 132 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 133 #define CONFIG_DDR_SPD 134 #undef CONFIG_DDR_DLL 135 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 137 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 138 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 142 #define CONFIG_NUM_DDR_CONTROLLERS 2 143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 144 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 145 146 /* I2C addresses of SPD EEPROMs */ 147 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 148 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 149 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 150 151 /* These are used when DDR doesn't use SPD. */ 152 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 153 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 154 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 155 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 156 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 157 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 158 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 159 #define CONFIG_SYS_DDR_MODE_1 0x00440462 160 #define CONFIG_SYS_DDR_MODE_2 0x00000000 161 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 162 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 163 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 164 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 165 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 166 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 167 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 168 169 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 170 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 171 #define CONFIG_SYS_DDR_SBE 0x00010000 172 173 /* 174 * Make sure required options are set 175 */ 176 #ifndef CONFIG_SPD_EEPROM 177 #error ("CONFIG_SPD_EEPROM is required") 178 #endif 179 180 #undef CONFIG_CLOCKS_IN_MHZ 181 182 /* 183 * Memory map 184 * 185 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 186 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 187 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 188 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 189 * 190 * Localbus cacheable (TBD) 191 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 192 * 193 * Localbus non-cacheable 194 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 195 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 196 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 197 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 198 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 199 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 200 */ 201 202 /* 203 * Local Bus Definitions 204 */ 205 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 206 #ifdef CONFIG_PHYS_64BIT 207 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 208 #else 209 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 210 #endif 211 212 213 #define CONFIG_FLASH_BR_PRELIM \ 214 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 215 | BR_PS_16 | BR_V) 216 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 217 218 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 219 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 220 221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 222 #define CONFIG_SYS_FLASH_QUIET_TEST 223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 224 225 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 227 #undef CONFIG_SYS_FLASH_CHECKSUM 228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 230 231 #if defined(CONFIG_RAMBOOT_NAND) 232 #define CONFIG_SYS_RAMBOOT 233 #define CONFIG_SYS_EXTRA_ENV_RELOC 234 #else 235 #undef CONFIG_SYS_RAMBOOT 236 #endif 237 238 #define CONFIG_FLASH_CFI_DRIVER 239 #define CONFIG_SYS_FLASH_CFI 240 #define CONFIG_SYS_FLASH_EMPTY_INFO 241 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 242 243 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 244 245 #define CONFIG_HWCONFIG /* enable hwconfig */ 246 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 247 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 248 #ifdef CONFIG_PHYS_64BIT 249 #define PIXIS_BASE_PHYS 0xfffdf0000ull 250 #else 251 #define PIXIS_BASE_PHYS PIXIS_BASE 252 #endif 253 254 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 255 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 256 257 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 258 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 259 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 260 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 261 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 262 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 263 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 264 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 265 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 266 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 267 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 268 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 269 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 270 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 271 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 272 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 273 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 274 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 275 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 276 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 277 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 278 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 279 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 280 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 281 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 282 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 283 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 284 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 285 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 286 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 287 #define PIXIS_LED 0x25 /* LED Register */ 288 289 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 290 291 /* old pixis referenced names */ 292 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 293 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 294 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 295 #define PIXIS_VSPEED2_TSEC1SER 0x8 296 #define PIXIS_VSPEED2_TSEC2SER 0x4 297 #define PIXIS_VSPEED2_TSEC3SER 0x2 298 #define PIXIS_VSPEED2_TSEC4SER 0x1 299 #define PIXIS_VCFGEN1_TSEC1SER 0x20 300 #define PIXIS_VCFGEN1_TSEC2SER 0x20 301 #define PIXIS_VCFGEN1_TSEC3SER 0x20 302 #define PIXIS_VCFGEN1_TSEC4SER 0x20 303 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 304 | PIXIS_VSPEED2_TSEC2SER \ 305 | PIXIS_VSPEED2_TSEC3SER \ 306 | PIXIS_VSPEED2_TSEC4SER) 307 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 308 | PIXIS_VCFGEN1_TSEC2SER \ 309 | PIXIS_VCFGEN1_TSEC3SER \ 310 | PIXIS_VCFGEN1_TSEC4SER) 311 312 #define CONFIG_SYS_INIT_RAM_LOCK 1 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 314 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 315 316 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 317 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 318 319 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 320 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 321 322 #ifndef CONFIG_NAND_SPL 323 #define CONFIG_SYS_NAND_BASE 0xffa00000 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 326 #else 327 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 328 #endif 329 #else 330 #define CONFIG_SYS_NAND_BASE 0xfff00000 331 #ifdef CONFIG_PHYS_64BIT 332 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 333 #else 334 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 335 #endif 336 #endif 337 338 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 339 CONFIG_SYS_NAND_BASE + 0x40000, \ 340 CONFIG_SYS_NAND_BASE + 0x80000,\ 341 CONFIG_SYS_NAND_BASE + 0xC0000} 342 #define CONFIG_SYS_MAX_NAND_DEVICE 4 343 #define CONFIG_MTD_NAND_VERIFY_WRITE 344 #define CONFIG_CMD_NAND 1 345 #define CONFIG_NAND_FSL_ELBC 1 346 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 347 348 /* NAND boot: 4K NAND loader config */ 349 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 350 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 351 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 352 #define CONFIG_SYS_NAND_U_BOOT_START \ 353 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 354 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 355 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 356 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 357 358 359 /* NAND flash config */ 360 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 361 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 362 | BR_PS_8 /* Port Size = 8 bit */ \ 363 | BR_MS_FCM /* MSEL = FCM */ \ 364 | BR_V) /* valid */ 365 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 366 | OR_FCM_PGS /* Large Page*/ \ 367 | OR_FCM_CSCT \ 368 | OR_FCM_CST \ 369 | OR_FCM_CHT \ 370 | OR_FCM_SCY_1 \ 371 | OR_FCM_TRLX \ 372 | OR_FCM_EHTR) 373 374 #ifdef CONFIG_RAMBOOT_NAND 375 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 376 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 377 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 378 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 379 #else 380 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 381 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 382 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 383 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 384 #endif 385 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 386 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 387 | BR_PS_8 /* Port Size = 8 bit */ \ 388 | BR_MS_FCM /* MSEL = FCM */ \ 389 | BR_V) /* valid */ 390 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 391 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 392 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 393 | BR_PS_8 /* Port Size = 8 bit */ \ 394 | BR_MS_FCM /* MSEL = FCM */ \ 395 | BR_V) /* valid */ 396 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 397 398 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 399 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 400 | BR_PS_8 /* Port Size = 8 bit */ \ 401 | BR_MS_FCM /* MSEL = FCM */ \ 402 | BR_V) /* valid */ 403 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 404 405 406 /* Serial Port - controlled on board with jumper J8 407 * open - index 2 408 * shorted - index 1 409 */ 410 #define CONFIG_CONS_INDEX 1 411 #define CONFIG_SYS_NS16550 412 #define CONFIG_SYS_NS16550_SERIAL 413 #define CONFIG_SYS_NS16550_REG_SIZE 1 414 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 415 #ifdef CONFIG_NAND_SPL 416 #define CONFIG_NS16550_MIN_FUNCTIONS 417 #endif 418 419 #define CONFIG_SYS_BAUDRATE_TABLE \ 420 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 421 422 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 423 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 424 425 /* Use the HUSH parser */ 426 #define CONFIG_SYS_HUSH_PARSER 427 #ifdef CONFIG_SYS_HUSH_PARSER 428 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 429 #endif 430 431 /* 432 * Pass open firmware flat tree 433 */ 434 #define CONFIG_OF_LIBFDT 1 435 #define CONFIG_OF_BOARD_SETUP 1 436 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 437 438 /* new uImage format support */ 439 #define CONFIG_FIT 1 440 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 441 442 /* I2C */ 443 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 444 #define CONFIG_HARD_I2C /* I2C with hardware support */ 445 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 446 #define CONFIG_I2C_MULTI_BUS 447 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 448 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 449 #define CONFIG_SYS_I2C_SLAVE 0x7F 450 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 451 #define CONFIG_SYS_I2C_OFFSET 0x3000 452 #define CONFIG_SYS_I2C2_OFFSET 0x3100 453 454 /* 455 * I2C2 EEPROM 456 */ 457 #define CONFIG_ID_EEPROM 458 #ifdef CONFIG_ID_EEPROM 459 #define CONFIG_SYS_I2C_EEPROM_NXID 460 #endif 461 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 462 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 463 #define CONFIG_SYS_EEPROM_BUS_NUM 1 464 465 /* 466 * General PCI 467 * Memory space is mapped 1-1, but I/O space must start from 0. 468 */ 469 470 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 471 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 474 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 475 #else 476 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 477 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 478 #endif 479 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 480 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 481 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 482 #ifdef CONFIG_PHYS_64BIT 483 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 484 #else 485 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 486 #endif 487 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 488 489 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 490 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 491 #ifdef CONFIG_PHYS_64BIT 492 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 493 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 494 #else 495 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 496 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 497 #endif 498 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 499 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 500 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 501 #ifdef CONFIG_PHYS_64BIT 502 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 503 #else 504 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 505 #endif 506 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 507 508 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 509 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 510 #ifdef CONFIG_PHYS_64BIT 511 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 512 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 513 #else 514 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 515 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 516 #endif 517 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 518 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 519 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 522 #else 523 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 524 #endif 525 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 526 527 #if defined(CONFIG_PCI) 528 529 /*PCIE video card used*/ 530 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 531 532 /* video */ 533 #define CONFIG_VIDEO 534 535 #if defined(CONFIG_VIDEO) 536 #define CONFIG_BIOSEMU 537 #define CONFIG_CFB_CONSOLE 538 #define CONFIG_VIDEO_SW_CURSOR 539 #define CONFIG_VGA_AS_SINGLE_DEVICE 540 #define CONFIG_ATI_RADEON_FB 541 #define CONFIG_VIDEO_LOGO 542 /*#define CONFIG_CONSOLE_CURSOR*/ 543 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 544 #endif 545 546 #define CONFIG_NET_MULTI 547 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 548 549 #undef CONFIG_EEPRO100 550 #undef CONFIG_TULIP 551 #undef CONFIG_RTL8139 552 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 553 554 #ifndef CONFIG_PCI_PNP 555 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 556 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 557 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 558 #endif 559 560 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 561 #define CONFIG_DOS_PARTITION 562 #define CONFIG_SCSI_AHCI 563 564 #ifdef CONFIG_SCSI_AHCI 565 #define CONFIG_SATA_ULI5288 566 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 567 #define CONFIG_SYS_SCSI_MAX_LUN 1 568 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 569 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 570 #endif /* SCSI */ 571 572 #endif /* CONFIG_PCI */ 573 574 575 #if defined(CONFIG_TSEC_ENET) 576 577 #ifndef CONFIG_NET_MULTI 578 #define CONFIG_NET_MULTI 1 579 #endif 580 581 #define CONFIG_MII 1 /* MII PHY management */ 582 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 583 #define CONFIG_TSEC1 1 584 #define CONFIG_TSEC1_NAME "eTSEC1" 585 #define CONFIG_TSEC2 1 586 #define CONFIG_TSEC2_NAME "eTSEC2" 587 #define CONFIG_TSEC3 1 588 #define CONFIG_TSEC3_NAME "eTSEC3" 589 #define CONFIG_TSEC4 1 590 #define CONFIG_TSEC4_NAME "eTSEC4" 591 592 #define CONFIG_PIXIS_SGMII_CMD 593 #define CONFIG_FSL_SGMII_RISER 1 594 #define SGMII_RISER_PHY_OFFSET 0x1c 595 596 #ifdef CONFIG_FSL_SGMII_RISER 597 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 598 #endif 599 600 #define TSEC1_PHY_ADDR 0 601 #define TSEC2_PHY_ADDR 1 602 #define TSEC3_PHY_ADDR 2 603 #define TSEC4_PHY_ADDR 3 604 605 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 606 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 607 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 608 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 609 610 #define TSEC1_PHYIDX 0 611 #define TSEC2_PHYIDX 0 612 #define TSEC3_PHYIDX 0 613 #define TSEC4_PHYIDX 0 614 615 #define CONFIG_ETHPRIME "eTSEC1" 616 617 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 618 #endif /* CONFIG_TSEC_ENET */ 619 620 /* 621 * Environment 622 */ 623 624 #if defined(CONFIG_SYS_RAMBOOT) 625 #if defined(CONFIG_RAMBOOT_NAND) 626 #define CONFIG_ENV_IS_IN_NAND 1 627 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 628 #define CONFIG_ENV_OFFSET ((512 * 1024)\ 629 + CONFIG_SYS_NAND_BLOCK_SIZE) 630 #endif 631 632 #else 633 #define CONFIG_ENV_IS_IN_FLASH 1 634 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 635 #define CONFIG_ENV_ADDR 0xfff80000 636 #else 637 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 638 #endif 639 #define CONFIG_ENV_SIZE 0x2000 640 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 641 #endif 642 643 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 644 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 645 646 /* 647 * Command line configuration. 648 */ 649 #include <config_cmd_default.h> 650 651 #define CONFIG_CMD_IRQ 652 #define CONFIG_CMD_PING 653 #define CONFIG_CMD_I2C 654 #define CONFIG_CMD_MII 655 #define CONFIG_CMD_ELF 656 #define CONFIG_CMD_IRQ 657 #define CONFIG_CMD_SETEXPR 658 #define CONFIG_CMD_REGINFO 659 660 #if defined(CONFIG_PCI) 661 #define CONFIG_CMD_PCI 662 #define CONFIG_CMD_NET 663 #define CONFIG_CMD_SCSI 664 #define CONFIG_CMD_EXT2 665 #endif 666 667 #undef CONFIG_WATCHDOG /* watchdog disabled */ 668 669 /* 670 * Miscellaneous configurable options 671 */ 672 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 673 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 674 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 675 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 676 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 677 #if defined(CONFIG_CMD_KGDB) 678 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 679 #else 680 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 681 #endif 682 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 683 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 684 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 685 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 686 687 /* 688 * For booting Linux, the board info and command line data 689 * have to be in the first 16 MB of memory, since this is 690 * the maximum mapped by the Linux kernel during initialization. 691 */ 692 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 693 694 #if defined(CONFIG_CMD_KGDB) 695 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 696 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 697 #endif 698 699 /* 700 * Environment Configuration 701 */ 702 703 /* The mac addresses for all ethernet interface */ 704 #if defined(CONFIG_TSEC_ENET) 705 #define CONFIG_HAS_ETH0 706 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 707 #define CONFIG_HAS_ETH1 708 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 709 #define CONFIG_HAS_ETH2 710 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 711 #define CONFIG_HAS_ETH3 712 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 713 #endif 714 715 #define CONFIG_IPADDR 192.168.1.254 716 717 #define CONFIG_HOSTNAME unknown 718 #define CONFIG_ROOTPATH /opt/nfsroot 719 #define CONFIG_BOOTFILE uImage 720 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 721 722 #define CONFIG_SERVERIP 192.168.1.1 723 #define CONFIG_GATEWAYIP 192.168.1.1 724 #define CONFIG_NETMASK 255.255.255.0 725 726 /* default location for tftp and bootm */ 727 #define CONFIG_LOADADDR 1000000 728 729 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 730 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 731 732 #define CONFIG_BAUDRATE 115200 733 734 #define CONFIG_EXTRA_ENV_SETTINGS \ 735 "memctl_intlv_ctl=2\0" \ 736 "netdev=eth0\0" \ 737 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 738 "tftpflash=tftpboot $loadaddr $uboot; " \ 739 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 740 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 741 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 742 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 743 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 744 "consoledev=ttyS0\0" \ 745 "ramdiskaddr=2000000\0" \ 746 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 747 "fdtaddr=c00000\0" \ 748 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 749 "bdev=sda3\0" 750 751 #define CONFIG_HDBOOT \ 752 "setenv bootargs root=/dev/$bdev rw " \ 753 "console=$consoledev,$baudrate $othbootargs;" \ 754 "tftp $loadaddr $bootfile;" \ 755 "tftp $fdtaddr $fdtfile;" \ 756 "bootm $loadaddr - $fdtaddr" 757 758 #define CONFIG_NFSBOOTCOMMAND \ 759 "setenv bootargs root=/dev/nfs rw " \ 760 "nfsroot=$serverip:$rootpath " \ 761 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 762 "console=$consoledev,$baudrate $othbootargs;" \ 763 "tftp $loadaddr $bootfile;" \ 764 "tftp $fdtaddr $fdtfile;" \ 765 "bootm $loadaddr - $fdtaddr" 766 767 #define CONFIG_RAMBOOTCOMMAND \ 768 "setenv bootargs root=/dev/ram rw " \ 769 "console=$consoledev,$baudrate $othbootargs;" \ 770 "tftp $ramdiskaddr $ramdiskfile;" \ 771 "tftp $loadaddr $bootfile;" \ 772 "tftp $fdtaddr $fdtfile;" \ 773 "bootm $loadaddr $ramdiskaddr $fdtaddr" 774 775 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 776 777 #endif /* __CONFIG_H */ 778