167431059SAndy Fleming /* 2*5f7bbd13SKumar Gala * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. 367431059SAndy Fleming * 467431059SAndy Fleming * See file CREDITS for list of people who contributed to this 567431059SAndy Fleming * project. 667431059SAndy Fleming * 767431059SAndy Fleming * This program is free software; you can redistribute it and/or 867431059SAndy Fleming * modify it under the terms of the GNU General Public License as 967431059SAndy Fleming * published by the Free Software Foundation; either version 2 of 1067431059SAndy Fleming * the License, or (at your option) any later version. 1167431059SAndy Fleming * 1267431059SAndy Fleming * This program is distributed in the hope that it will be useful, 1367431059SAndy Fleming * but WITHOUT ANY WARRANTY; without even the implied warranty of 1467431059SAndy Fleming * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1567431059SAndy Fleming * GNU General Public License for more details. 1667431059SAndy Fleming * 1767431059SAndy Fleming * You should have received a copy of the GNU General Public License 1867431059SAndy Fleming * along with this program; if not, write to the Free Software 1967431059SAndy Fleming * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2067431059SAndy Fleming * MA 02111-1307 USA 2167431059SAndy Fleming */ 2267431059SAndy Fleming 2367431059SAndy Fleming /* 2467431059SAndy Fleming * mpc8568mds board configuration file 2567431059SAndy Fleming */ 2667431059SAndy Fleming #ifndef __CONFIG_H 2767431059SAndy Fleming #define __CONFIG_H 2867431059SAndy Fleming 2967431059SAndy Fleming /* High Level Configuration Options */ 3067431059SAndy Fleming #define CONFIG_BOOKE 1 /* BOOKE */ 3167431059SAndy Fleming #define CONFIG_E500 1 /* BOOKE e500 family */ 3267431059SAndy Fleming #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 3367431059SAndy Fleming #define CONFIG_MPC8568 1 /* MPC8568 specific */ 3467431059SAndy Fleming #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ 3567431059SAndy Fleming 362ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xfff80000 372ae18241SWolfgang Denk 38*5f7bbd13SKumar Gala #define CONFIG_SYS_SRIO 39*5f7bbd13SKumar Gala #define CONFIG_SRIO1 /* SRIO port 1 */ 40*5f7bbd13SKumar Gala 411563f56eSHaiying Wang #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 421563f56eSHaiying Wang #define CONFIG_PCI1 1 /* PCI controller */ 431563f56eSHaiying Wang #define CONFIG_PCIE1 1 /* PCIE controller */ 441563f56eSHaiying Wang #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 458ff3de61SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 460151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 4767431059SAndy Fleming #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48b96c83d4SAndy Fleming #define CONFIG_QE /* Enable QE */ 4967431059SAndy Fleming #define CONFIG_ENV_OVERWRITE 504d3521ccSKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 5167431059SAndy Fleming 5267431059SAndy Fleming #ifndef __ASSEMBLY__ 5367431059SAndy Fleming extern unsigned long get_clock_freq(void); 5467431059SAndy Fleming #endif /*Replace a call to get_clock_freq (after it is implemented)*/ 5567431059SAndy Fleming #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ 5667431059SAndy Fleming 5767431059SAndy Fleming /* 5867431059SAndy Fleming * These can be toggled for performance analysis, otherwise use default. 5967431059SAndy Fleming */ 607a1ac419SHaiying Wang #define CONFIG_L2_CACHE /* toggle L2 cache */ 6167431059SAndy Fleming #define CONFIG_BTB /* toggle branch predition */ 6267431059SAndy Fleming 6367431059SAndy Fleming /* 6467431059SAndy Fleming * Only possible on E500 Version 2 or newer cores. 6567431059SAndy Fleming */ 6667431059SAndy Fleming #define CONFIG_ENABLE_36BIT_PHYS 1 6767431059SAndy Fleming 6867431059SAndy Fleming 6967431059SAndy Fleming #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 7067431059SAndy Fleming 716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x00400000 7367431059SAndy Fleming 7467431059SAndy Fleming /* 7567431059SAndy Fleming * Base addresses -- Note these are effective addresses where the 7667431059SAndy Fleming * actual resources get mapped (not physical addresses) 7767431059SAndy Fleming */ 786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 8267431059SAndy Fleming 83e6f5b35bSJon Loeliger /* DDR Setup */ 84e6f5b35bSJon Loeliger #define CONFIG_FSL_DDR2 85e6f5b35bSJon Loeliger #undef CONFIG_FSL_DDR_INTERACTIVE 86e6f5b35bSJon Loeliger #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 87e6f5b35bSJon Loeliger #define CONFIG_DDR_SPD 889b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 89e6f5b35bSJon Loeliger 90e6f5b35bSJon Loeliger #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 91e6f5b35bSJon Loeliger 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 9467431059SAndy Fleming 95e6f5b35bSJon Loeliger #define CONFIG_NUM_DDR_CONTROLLERS 1 96e6f5b35bSJon Loeliger #define CONFIG_DIMM_SLOTS_PER_CTLR 1 97e6f5b35bSJon Loeliger #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 9867431059SAndy Fleming 99e6f5b35bSJon Loeliger /* I2C addresses of SPD EEPROMs */ 100e6f5b35bSJon Loeliger #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 101e6f5b35bSJon Loeliger 102e6f5b35bSJon Loeliger /* Make sure required options are set */ 10367431059SAndy Fleming #ifndef CONFIG_SPD_EEPROM 10467431059SAndy Fleming #error ("CONFIG_SPD_EEPROM is required") 10567431059SAndy Fleming #endif 10667431059SAndy Fleming 10767431059SAndy Fleming #undef CONFIG_CLOCKS_IN_MHZ 10867431059SAndy Fleming 10967431059SAndy Fleming /* 11067431059SAndy Fleming * Local Bus Definitions 11167431059SAndy Fleming */ 11267431059SAndy Fleming 11367431059SAndy Fleming /* 11467431059SAndy Fleming * FLASH on the Local Bus 11567431059SAndy Fleming * Two banks, 8M each, using the CFI driver. 11667431059SAndy Fleming * Boot from BR0/OR0 bank at 0xff00_0000 11767431059SAndy Fleming * Alternate BR1/OR1 bank at 0xff80_0000 11867431059SAndy Fleming * 11967431059SAndy Fleming * BR0, BR1: 12067431059SAndy Fleming * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 12167431059SAndy Fleming * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 12267431059SAndy Fleming * Port Size = 16 bits = BRx[19:20] = 10 12367431059SAndy Fleming * Use GPCM = BRx[24:26] = 000 12467431059SAndy Fleming * Valid = BRx[31] = 1 12567431059SAndy Fleming * 12667431059SAndy Fleming * 0 4 8 12 16 20 24 28 12767431059SAndy Fleming * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 12867431059SAndy Fleming * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 12967431059SAndy Fleming * 13067431059SAndy Fleming * OR0, OR1: 13167431059SAndy Fleming * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 13267431059SAndy Fleming * Reserved ORx[17:18] = 11, confusion here? 13367431059SAndy Fleming * CSNT = ORx[20] = 1 13467431059SAndy Fleming * ACS = half cycle delay = ORx[21:22] = 11 13567431059SAndy Fleming * SCY = 6 = ORx[24:27] = 0110 13667431059SAndy Fleming * TRLX = use relaxed timing = ORx[29] = 1 13767431059SAndy Fleming * EAD = use external address latch delay = OR[31] = 1 13867431059SAndy Fleming * 13967431059SAndy Fleming * 0 4 8 12 16 20 24 28 14067431059SAndy Fleming * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 14167431059SAndy Fleming */ 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BCSR_BASE 0xf8000000 14367431059SAndy Fleming 1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 14567431059SAndy Fleming 14667431059SAndy Fleming /*Chip select 0 - Flash*/ 1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM 0xfe001001 1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 14967431059SAndy Fleming 15067431059SAndy Fleming /*Chip slelect 1 - BCSR*/ 1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM 0xf8000801 1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 15367431059SAndy Fleming 1546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ 1556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 1566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 16067431059SAndy Fleming 16114d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 16267431059SAndy Fleming 16300b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER 1646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 16667431059SAndy Fleming 16767431059SAndy Fleming 16867431059SAndy Fleming /* 16967431059SAndy Fleming * SDRAM on the LocalBus 17067431059SAndy Fleming */ 1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 17367431059SAndy Fleming 17467431059SAndy Fleming 17567431059SAndy Fleming /*Chip select 2 - SDRAM*/ 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM 0xf0001861 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM 0xfc006901 17867431059SAndy Fleming 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 18367431059SAndy Fleming 18467431059SAndy Fleming /* 18567431059SAndy Fleming * Common settings for all Local Bus SDRAM commands. 18667431059SAndy Fleming * At run time, either BSMA1516 (for CPU 1.1) 18767431059SAndy Fleming * or BSMA1617 (for CPU 1.0) (old) 18867431059SAndy Fleming * is OR'ed in too. 18967431059SAndy Fleming */ 190b0fe93edSKumar Gala #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 191b0fe93edSKumar Gala | LSDMR_PRETOACT7 \ 192b0fe93edSKumar Gala | LSDMR_ACTTORW7 \ 193b0fe93edSKumar Gala | LSDMR_BL8 \ 194b0fe93edSKumar Gala | LSDMR_WRC4 \ 195b0fe93edSKumar Gala | LSDMR_CL3 \ 196b0fe93edSKumar Gala | LSDMR_RFEN \ 19767431059SAndy Fleming ) 19867431059SAndy Fleming 19967431059SAndy Fleming /* 20067431059SAndy Fleming * The bcsr registers are connected to CS3 on MDS. 20167431059SAndy Fleming * The new memory map places bcsr at 0xf8000000. 20267431059SAndy Fleming * 20367431059SAndy Fleming * For BR3, need: 20467431059SAndy Fleming * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 20567431059SAndy Fleming * port-size = 8-bits = BR[19:20] = 01 20667431059SAndy Fleming * no parity checking = BR[21:22] = 00 20767431059SAndy Fleming * GPMC for MSEL = BR[24:26] = 000 20867431059SAndy Fleming * Valid = BR[31] = 1 20967431059SAndy Fleming * 21067431059SAndy Fleming * 0 4 8 12 16 20 24 28 21167431059SAndy Fleming * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 21267431059SAndy Fleming * 21367431059SAndy Fleming * For OR3, need: 21467431059SAndy Fleming * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 21567431059SAndy Fleming * disable buffer ctrl OR[19] = 0 21667431059SAndy Fleming * CSNT OR[20] = 1 21767431059SAndy Fleming * ACS OR[21:22] = 11 21867431059SAndy Fleming * XACS OR[23] = 1 21967431059SAndy Fleming * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 22067431059SAndy Fleming * SETA OR[28] = 0 22167431059SAndy Fleming * TRLX OR[29] = 1 22267431059SAndy Fleming * EHTR OR[30] = 1 22367431059SAndy Fleming * EAD extra time OR[31] = 1 22467431059SAndy Fleming * 22567431059SAndy Fleming * 0 4 8 12 16 20 24 28 22667431059SAndy Fleming * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 22767431059SAndy Fleming */ 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BCSR (0xf8000000) 22967431059SAndy Fleming 23067431059SAndy Fleming /*Chip slelect 4 - PIB*/ 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR4_PRELIM 0xf8008801 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 23367431059SAndy Fleming 23467431059SAndy Fleming /*Chip select 5 - PIB*/ 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR5_PRELIM 0xf8010801 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 23767431059SAndy Fleming 2386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 240553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 24167431059SAndy Fleming 24225ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 24467431059SAndy Fleming 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 24767431059SAndy Fleming 24867431059SAndy Fleming /* Serial Port */ 24967431059SAndy Fleming #define CONFIG_CONS_INDEX 1 2506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 2516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 2536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 25467431059SAndy Fleming 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 25667431059SAndy Fleming {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 25767431059SAndy Fleming 2586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 26067431059SAndy Fleming 26167431059SAndy Fleming /* Use the HUSH parser*/ 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 2636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 26567431059SAndy Fleming #endif 26667431059SAndy Fleming 26767431059SAndy Fleming /* pass open firmware flat tree */ 268c480861bSKumar Gala #define CONFIG_OF_LIBFDT 1 26967431059SAndy Fleming #define CONFIG_OF_BOARD_SETUP 1 270c480861bSKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 27167431059SAndy Fleming 27267431059SAndy Fleming /* 27367431059SAndy Fleming * I2C 27467431059SAndy Fleming */ 27567431059SAndy Fleming #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 27667431059SAndy Fleming #define CONFIG_HARD_I2C /* I2C with hardware support*/ 27767431059SAndy Fleming #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 278c59e4091SHaiying Wang #define CONFIG_I2C_MULTI_BUS 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 2826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 28567431059SAndy Fleming 28667431059SAndy Fleming /* 28767431059SAndy Fleming * General PCI 28867431059SAndy Fleming * Memory Addresses are mapped 1-1. I/O is mapped from 0 28967431059SAndy Fleming */ 2905af0fdd8SKumar Gala #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 29110795f42SKumar Gala #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 2925af0fdd8SKumar Gala #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 294aca5f018SKumar Gala #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 2955f91ef6aSKumar Gala #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 29867431059SAndy Fleming 2993f6f9d76SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot" 3005af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 30110795f42SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 3025af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 304aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 3055f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 30867431059SAndy Fleming 309*5f7bbd13SKumar Gala #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 310*5f7bbd13SKumar Gala #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 311*5f7bbd13SKumar Gala #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 312*5f7bbd13SKumar Gala #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 31367431059SAndy Fleming 314da9d4610SAndy Fleming #ifdef CONFIG_QE 315da9d4610SAndy Fleming /* 316da9d4610SAndy Fleming * QE UEC ethernet configuration 317da9d4610SAndy Fleming */ 318da9d4610SAndy Fleming #define CONFIG_UEC_ETH 319da9d4610SAndy Fleming #ifndef CONFIG_TSEC_ENET 32078b7a8efSKim Phillips #define CONFIG_ETHPRIME "UEC0" 321da9d4610SAndy Fleming #endif 322da9d4610SAndy Fleming #define CONFIG_PHY_MODE_NEED_CHANGE 323da9d4610SAndy Fleming #define CONFIG_eTSEC_MDIO_BUS 324da9d4610SAndy Fleming 325da9d4610SAndy Fleming #ifdef CONFIG_eTSEC_MDIO_BUS 326da9d4610SAndy Fleming #define CONFIG_MIIM_ADDRESS 0xE0024520 327da9d4610SAndy Fleming #endif 328da9d4610SAndy Fleming 329da9d4610SAndy Fleming #define CONFIG_UEC_ETH1 /* GETH1 */ 330da9d4610SAndy Fleming 331da9d4610SAndy Fleming #ifdef CONFIG_UEC_ETH1 3326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 3336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 3346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC1_PHY_ADDR 7 337582c55a0SHeiko Schocher #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID 338582c55a0SHeiko Schocher #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 339da9d4610SAndy Fleming #endif 340da9d4610SAndy Fleming 341da9d4610SAndy Fleming #define CONFIG_UEC_ETH2 /* GETH2 */ 342da9d4610SAndy Fleming 343da9d4610SAndy Fleming #ifdef CONFIG_UEC_ETH2 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_UEC2_PHY_ADDR 1 349582c55a0SHeiko Schocher #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID 350582c55a0SHeiko Schocher #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 351da9d4610SAndy Fleming #endif 352da9d4610SAndy Fleming #endif /* CONFIG_QE */ 353da9d4610SAndy Fleming 354f30ad49bSHaiying Wang #if defined(CONFIG_PCI) 355f30ad49bSHaiying Wang 356f30ad49bSHaiying Wang #define CONFIG_NET_MULTI 357f30ad49bSHaiying Wang #define CONFIG_PCI_PNP /* do pci plug-and-play */ 358f30ad49bSHaiying Wang 35967431059SAndy Fleming #undef CONFIG_EEPRO100 36067431059SAndy Fleming #undef CONFIG_TULIP 36167431059SAndy Fleming 36267431059SAndy Fleming #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 36467431059SAndy Fleming 36567431059SAndy Fleming #endif /* CONFIG_PCI */ 36667431059SAndy Fleming 36767431059SAndy Fleming #ifndef CONFIG_NET_MULTI 36867431059SAndy Fleming #define CONFIG_NET_MULTI 1 36967431059SAndy Fleming #endif 37067431059SAndy Fleming 371da9d4610SAndy Fleming #if defined(CONFIG_TSEC_ENET) 372da9d4610SAndy Fleming 37367431059SAndy Fleming #define CONFIG_MII 1 /* MII PHY management */ 374255a3577SKim Phillips #define CONFIG_TSEC1 1 375255a3577SKim Phillips #define CONFIG_TSEC1_NAME "eTSEC0" 376255a3577SKim Phillips #define CONFIG_TSEC2 1 377255a3577SKim Phillips #define CONFIG_TSEC2_NAME "eTSEC1" 37867431059SAndy Fleming 37967431059SAndy Fleming #define TSEC1_PHY_ADDR 2 38067431059SAndy Fleming #define TSEC2_PHY_ADDR 3 38167431059SAndy Fleming 38267431059SAndy Fleming #define TSEC1_PHYIDX 0 38367431059SAndy Fleming #define TSEC2_PHYIDX 0 38467431059SAndy Fleming 3853a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 3863a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 3873a79013eSAndy Fleming 388b96c83d4SAndy Fleming /* Options are: eTSEC[0-1] */ 38967431059SAndy Fleming #define CONFIG_ETHPRIME "eTSEC0" 39067431059SAndy Fleming 39167431059SAndy Fleming #endif /* CONFIG_TSEC_ENET */ 39267431059SAndy Fleming 39367431059SAndy Fleming /* 39467431059SAndy Fleming * Environment 39567431059SAndy Fleming */ 3965a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 3980e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 3990e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 40067431059SAndy Fleming 40167431059SAndy Fleming #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 40367431059SAndy Fleming 4042835e518SJon Loeliger 4052835e518SJon Loeliger /* 406079a136cSJon Loeliger * BOOTP options 407079a136cSJon Loeliger */ 408079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 409079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 410079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 411079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 412079a136cSJon Loeliger 413079a136cSJon Loeliger 414079a136cSJon Loeliger /* 4152835e518SJon Loeliger * Command line configuration. 4162835e518SJon Loeliger */ 4172835e518SJon Loeliger #include <config_cmd_default.h> 4182835e518SJon Loeliger 4192835e518SJon Loeliger #define CONFIG_CMD_PING 4202835e518SJon Loeliger #define CONFIG_CMD_I2C 4212835e518SJon Loeliger #define CONFIG_CMD_MII 42282ac8c97SKumar Gala #define CONFIG_CMD_ELF 4231c9aa76bSKumar Gala #define CONFIG_CMD_IRQ 4241c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 425199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 4262835e518SJon Loeliger 42767431059SAndy Fleming #if defined(CONFIG_PCI) 4282835e518SJon Loeliger #define CONFIG_CMD_PCI 42967431059SAndy Fleming #endif 4302835e518SJon Loeliger 43167431059SAndy Fleming 43267431059SAndy Fleming #undef CONFIG_WATCHDOG /* watchdog disabled */ 43367431059SAndy Fleming 43467431059SAndy Fleming /* 43567431059SAndy Fleming * Miscellaneous configurable options 43667431059SAndy Fleming */ 4376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 43822abb2d2SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 4395be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 4406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 4422835e518SJon Loeliger #if defined(CONFIG_CMD_KGDB) 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 44467431059SAndy Fleming #else 4456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 44667431059SAndy Fleming #endif 4476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 4496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 4506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 45167431059SAndy Fleming 45267431059SAndy Fleming /* 45367431059SAndy Fleming * For booting Linux, the board info and command line data 45489188a62SKumar Gala * have to be in the first 16 MB of memory, since this is 45567431059SAndy Fleming * the maximum mapped by the Linux kernel during initialization. 45667431059SAndy Fleming */ 45789188a62SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 45867431059SAndy Fleming 4592835e518SJon Loeliger #if defined(CONFIG_CMD_KGDB) 46067431059SAndy Fleming #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 46167431059SAndy Fleming #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 46267431059SAndy Fleming #endif 46367431059SAndy Fleming 46467431059SAndy Fleming /* 46567431059SAndy Fleming * Environment Configuration 46667431059SAndy Fleming */ 46767431059SAndy Fleming 46867431059SAndy Fleming /* The mac addresses for all ethernet interface */ 469da9d4610SAndy Fleming #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) 470da9d4610SAndy Fleming #define CONFIG_HAS_ETH0 47167431059SAndy Fleming #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 47267431059SAndy Fleming #define CONFIG_HAS_ETH1 47367431059SAndy Fleming #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 47467431059SAndy Fleming #define CONFIG_HAS_ETH2 47567431059SAndy Fleming #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 476da9d4610SAndy Fleming #define CONFIG_HAS_ETH3 477da9d4610SAndy Fleming #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 47867431059SAndy Fleming #endif 47967431059SAndy Fleming 48067431059SAndy Fleming #define CONFIG_IPADDR 192.168.1.253 48167431059SAndy Fleming 48267431059SAndy Fleming #define CONFIG_HOSTNAME unknown 48367431059SAndy Fleming #define CONFIG_ROOTPATH /nfsroot 48467431059SAndy Fleming #define CONFIG_BOOTFILE your.uImage 48567431059SAndy Fleming 48667431059SAndy Fleming #define CONFIG_SERVERIP 192.168.1.1 48767431059SAndy Fleming #define CONFIG_GATEWAYIP 192.168.1.1 48867431059SAndy Fleming #define CONFIG_NETMASK 255.255.255.0 48967431059SAndy Fleming 49067431059SAndy Fleming #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 49167431059SAndy Fleming 49267431059SAndy Fleming #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 49367431059SAndy Fleming #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 49467431059SAndy Fleming 49567431059SAndy Fleming #define CONFIG_BAUDRATE 115200 49667431059SAndy Fleming 49767431059SAndy Fleming #define CONFIG_EXTRA_ENV_SETTINGS \ 49867431059SAndy Fleming "netdev=eth0\0" \ 49967431059SAndy Fleming "consoledev=ttyS0\0" \ 50067431059SAndy Fleming "ramdiskaddr=600000\0" \ 50167431059SAndy Fleming "ramdiskfile=your.ramdisk.u-boot\0" \ 50267431059SAndy Fleming "fdtaddr=400000\0" \ 50367431059SAndy Fleming "fdtfile=your.fdt.dtb\0" \ 50467431059SAndy Fleming "nfsargs=setenv bootargs root=/dev/nfs rw " \ 50567431059SAndy Fleming "nfsroot=$serverip:$rootpath " \ 50667431059SAndy Fleming "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 50767431059SAndy Fleming "console=$consoledev,$baudrate $othbootargs\0" \ 50867431059SAndy Fleming "ramargs=setenv bootargs root=/dev/ram rw " \ 50967431059SAndy Fleming "console=$consoledev,$baudrate $othbootargs\0" \ 51067431059SAndy Fleming 51167431059SAndy Fleming 51267431059SAndy Fleming #define CONFIG_NFSBOOTCOMMAND \ 51367431059SAndy Fleming "run nfsargs;" \ 51467431059SAndy Fleming "tftp $loadaddr $bootfile;" \ 51567431059SAndy Fleming "tftp $fdtaddr $fdtfile;" \ 51667431059SAndy Fleming "bootm $loadaddr - $fdtaddr" 51767431059SAndy Fleming 51867431059SAndy Fleming 51967431059SAndy Fleming #define CONFIG_RAMBOOTCOMMAND \ 52067431059SAndy Fleming "run ramargs;" \ 52167431059SAndy Fleming "tftp $ramdiskaddr $ramdiskfile;" \ 52267431059SAndy Fleming "tftp $loadaddr $bootfile;" \ 52367431059SAndy Fleming "bootm $loadaddr $ramdiskaddr" 52467431059SAndy Fleming 52567431059SAndy Fleming #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 52667431059SAndy Fleming 52767431059SAndy Fleming #endif /* __CONFIG_H */ 528