1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8544ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_BOOKE 1 /* BOOKE */ 16 #define CONFIG_E500 1 /* BOOKE e500 family */ 17 18 #ifndef CONFIG_SYS_TEXT_BASE 19 #define CONFIG_SYS_TEXT_BASE 0xfff80000 20 #endif 21 22 #define CONFIG_PCI1 1 /* PCI controller 1 */ 23 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 24 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 25 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 26 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 28 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 31 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 32 33 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 34 #define CONFIG_ENV_OVERWRITE 35 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 36 37 #ifndef __ASSEMBLY__ 38 extern unsigned long get_board_sys_clk(unsigned long dummy); 39 #endif 40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 41 42 /* 43 * These can be toggled for performance analysis, otherwise use default. 44 */ 45 #define CONFIG_L2_CACHE /* toggle L2 cache */ 46 #define CONFIG_BTB /* toggle branch predition */ 47 48 /* 49 * Only possible on E500 Version 2 or newer cores. 50 */ 51 #define CONFIG_ENABLE_36BIT_PHYS 1 52 53 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 54 #define CONFIG_SYS_MEMTEST_END 0x00400000 55 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 56 57 #define CONFIG_SYS_CCSRBAR 0xe0000000 58 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 59 60 /* DDR Setup */ 61 #define CONFIG_SYS_FSL_DDR2 62 #undef CONFIG_FSL_DDR_INTERACTIVE 63 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 64 #define CONFIG_DDR_SPD 65 66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 67 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 68 69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 71 #define CONFIG_VERY_BIG_RAM 72 73 #define CONFIG_NUM_DDR_CONTROLLERS 1 74 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 75 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 76 77 /* I2C addresses of SPD EEPROMs */ 78 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 79 80 /* Make sure required options are set */ 81 #ifndef CONFIG_SPD_EEPROM 82 #error ("CONFIG_SPD_EEPROM is required") 83 #endif 84 85 #undef CONFIG_CLOCKS_IN_MHZ 86 87 /* 88 * Memory map 89 * 90 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 91 * 92 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 93 * 94 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 95 * 96 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 97 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 98 * 99 * Localbus cacheable 100 * 101 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable 102 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 103 * 104 * Localbus non-cacheable 105 * 106 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable 107 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 108 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 109 * 110 */ 111 112 /* 113 * Local Bus Definitions 114 */ 115 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ 116 117 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ 118 119 #define CONFIG_SYS_BR0_PRELIM 0xff801001 120 #define CONFIG_SYS_BR1_PRELIM 0xfe801001 121 122 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 123 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 124 125 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 126 127 #define CONFIG_SYS_FLASH_QUIET_TEST 128 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 129 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 130 #undef CONFIG_SYS_FLASH_CHECKSUM 131 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 132 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 133 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 134 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 136 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_EMPTY_INFO 140 141 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 142 143 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ 144 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 145 146 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ 147 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 148 149 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 150 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 151 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 152 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 153 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 154 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 155 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch 156 * register */ 157 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 158 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 159 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 160 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 161 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 162 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 163 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 164 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 165 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 166 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 167 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 168 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ 169 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 170 #define PIXIS_VSPEED2_TSEC1SER 0x2 171 #define PIXIS_VSPEED2_TSEC3SER 0x1 172 #define PIXIS_VCFGEN1_TSEC1SER 0x20 173 #define PIXIS_VCFGEN1_TSEC3SER 0x40 174 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) 175 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) 176 177 #define CONFIG_SYS_INIT_RAM_LOCK 1 178 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ 179 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 180 181 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183 184 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 185 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 186 187 /* Serial Port - controlled on board with jumper J8 188 * open - index 2 189 * shorted - index 1 190 */ 191 #define CONFIG_CONS_INDEX 1 192 #define CONFIG_SYS_NS16550_SERIAL 193 #define CONFIG_SYS_NS16550_REG_SIZE 1 194 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 195 196 #define CONFIG_SYS_BAUDRATE_TABLE \ 197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 198 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 201 202 /* I2C */ 203 #define CONFIG_SYS_I2C 204 #define CONFIG_SYS_I2C_FSL 205 #define CONFIG_SYS_FSL_I2C_SPEED 400000 206 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 207 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 208 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 209 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 210 211 /* 212 * General PCI 213 * Memory space is mapped 1-1, but I/O space must start from 0. 214 */ 215 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ 216 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ 217 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ 218 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ 219 220 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 221 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 222 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 223 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 224 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 225 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 226 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 227 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 228 229 /* controller 2, Slot 1, tgtid 1, Base address 9000 */ 230 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 231 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 232 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 233 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 234 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 235 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 236 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 237 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 238 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 239 240 /* controller 1, Slot 2,tgtid 2, Base address a000 */ 241 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 242 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 243 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 244 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 245 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 246 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 247 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 248 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 249 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 250 251 /* controller 3, direct to uli, tgtid 3, Base address b000 */ 252 #define CONFIG_SYS_PCIE3_NAME "ULI" 253 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 254 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 255 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 256 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ 257 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ 258 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 259 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ 260 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ 261 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 262 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 263 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 264 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ 265 266 #if defined(CONFIG_PCI) 267 268 /*PCIE video card used*/ 269 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 270 271 /*PCI video card used*/ 272 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 273 274 /* video */ 275 276 #if defined(CONFIG_VIDEO) 277 #define CONFIG_BIOSEMU 278 #define CONFIG_ATI_RADEON_FB 279 #define CONFIG_VIDEO_LOGO 280 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 281 #endif 282 283 #undef CONFIG_EEPRO100 284 #undef CONFIG_TULIP 285 286 #ifndef CONFIG_PCI_PNP 287 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 288 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 289 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 290 #endif 291 292 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 293 #define CONFIG_DOS_PARTITION 294 #define CONFIG_SCSI_AHCI 295 296 #ifdef CONFIG_SCSI_AHCI 297 #define CONFIG_LIBATA 298 #define CONFIG_SATA_ULI5288 299 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 300 #define CONFIG_SYS_SCSI_MAX_LUN 1 301 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 302 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 303 #endif /* SCSCI */ 304 305 #endif /* CONFIG_PCI */ 306 307 #if defined(CONFIG_TSEC_ENET) 308 309 #define CONFIG_MII 1 /* MII PHY management */ 310 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 311 #define CONFIG_TSEC1 1 312 #define CONFIG_TSEC1_NAME "eTSEC1" 313 #define CONFIG_TSEC3 1 314 #define CONFIG_TSEC3_NAME "eTSEC3" 315 316 #define CONFIG_PIXIS_SGMII_CMD 317 #define CONFIG_FSL_SGMII_RISER 1 318 #define SGMII_RISER_PHY_OFFSET 0x1c 319 320 #define TSEC1_PHY_ADDR 0 321 #define TSEC3_PHY_ADDR 1 322 323 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 324 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 325 326 #define TSEC1_PHYIDX 0 327 #define TSEC3_PHYIDX 0 328 329 #define CONFIG_ETHPRIME "eTSEC1" 330 331 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 332 #endif /* CONFIG_TSEC_ENET */ 333 334 /* 335 * Environment 336 */ 337 #define CONFIG_ENV_IS_IN_FLASH 1 338 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 339 #define CONFIG_ENV_ADDR 0xfff80000 340 #else 341 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 342 #endif 343 #define CONFIG_ENV_SIZE 0x2000 344 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ 345 346 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 347 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 348 349 /* 350 * BOOTP options 351 */ 352 #define CONFIG_BOOTP_BOOTFILESIZE 353 #define CONFIG_BOOTP_BOOTPATH 354 #define CONFIG_BOOTP_GATEWAY 355 #define CONFIG_BOOTP_HOSTNAME 356 357 /* 358 * Command line configuration. 359 */ 360 #define CONFIG_CMD_IRQ 361 #define CONFIG_CMD_REGINFO 362 363 #if defined(CONFIG_PCI) 364 #define CONFIG_CMD_PCI 365 #define CONFIG_SCSI 366 #endif 367 368 /* 369 * USB 370 */ 371 #define CONFIG_USB_EHCI 372 373 #ifdef CONFIG_USB_EHCI 374 #define CONFIG_USB_EHCI_PCI 375 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 376 #define CONFIG_PCI_EHCI_DEVICE 0 377 #endif 378 379 #undef CONFIG_WATCHDOG /* watchdog disabled */ 380 381 /* 382 * Miscellaneous configurable options 383 */ 384 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 385 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 386 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 387 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 388 #if defined(CONFIG_CMD_KGDB) 389 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 390 #else 391 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 392 #endif 393 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 394 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 395 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 396 397 /* 398 * For booting Linux, the board info and command line data 399 * have to be in the first 64 MB of memory, since this is 400 * the maximum mapped by the Linux kernel during initialization. 401 */ 402 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 403 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 404 405 #if defined(CONFIG_CMD_KGDB) 406 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 407 #endif 408 409 /* 410 * Environment Configuration 411 */ 412 413 /* The mac addresses for all ethernet interface */ 414 #if defined(CONFIG_TSEC_ENET) 415 #define CONFIG_HAS_ETH0 416 #define CONFIG_HAS_ETH1 417 #endif 418 419 #define CONFIG_IPADDR 192.168.1.251 420 421 #define CONFIG_HOSTNAME 8544ds_unknown 422 #define CONFIG_ROOTPATH "/nfs/mpc85xx" 423 #define CONFIG_BOOTFILE "8544ds/uImage.uboot" 424 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ 425 426 #define CONFIG_SERVERIP 192.168.1.1 427 #define CONFIG_GATEWAYIP 192.168.1.1 428 #define CONFIG_NETMASK 255.255.0.0 429 430 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 431 432 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 433 434 #define CONFIG_BAUDRATE 115200 435 436 #define CONFIG_EXTRA_ENV_SETTINGS \ 437 "netdev=eth0\0" \ 438 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 439 "tftpflash=tftpboot $loadaddr $uboot; " \ 440 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 441 " +$filesize; " \ 442 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 443 " +$filesize; " \ 444 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 445 " $filesize; " \ 446 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 447 " +$filesize; " \ 448 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 449 " $filesize\0" \ 450 "consoledev=ttyS0\0" \ 451 "ramdiskaddr=2000000\0" \ 452 "ramdiskfile=8544ds/ramdisk.uboot\0" \ 453 "fdtaddr=1e00000\0" \ 454 "fdtfile=8544ds/mpc8544ds.dtb\0" \ 455 "bdev=sda3\0" 456 457 #define CONFIG_NFSBOOTCOMMAND \ 458 "setenv bootargs root=/dev/nfs rw " \ 459 "nfsroot=$serverip:$rootpath " \ 460 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 461 "console=$consoledev,$baudrate $othbootargs;" \ 462 "tftp $loadaddr $bootfile;" \ 463 "tftp $fdtaddr $fdtfile;" \ 464 "bootm $loadaddr - $fdtaddr" 465 466 #define CONFIG_RAMBOOTCOMMAND \ 467 "setenv bootargs root=/dev/ram rw " \ 468 "console=$consoledev,$baudrate $othbootargs;" \ 469 "tftp $ramdiskaddr $ramdiskfile;" \ 470 "tftp $loadaddr $bootfile;" \ 471 "tftp $fdtaddr $fdtfile;" \ 472 "bootm $loadaddr $ramdiskaddr $fdtaddr" 473 474 #define CONFIG_BOOTCOMMAND \ 475 "setenv bootargs root=/dev/$bdev rw " \ 476 "console=$consoledev,$baudrate $othbootargs;" \ 477 "tftp $loadaddr $bootfile;" \ 478 "tftp $fdtaddr $fdtfile;" \ 479 "bootm $loadaddr - $fdtaddr" 480 481 #endif /* __CONFIG_H */ 482