1 /* 2 * Copyright 2004, 2011 Freescale Semiconductor. 3 * (C) Copyright 2002,2003 Motorola,Inc. 4 * Xianghua Xiao <X.Xiao@motorola.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * mpc8540ads board configuration file 27 * 28 * Please refer to doc/README.mpc85xx for more info. 29 * 30 * Make sure you change the MAC address and other network params first, 31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 1 /* BOOKE */ 39 #define CONFIG_E500 1 /* BOOKE e500 family */ 40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 41 #define CONFIG_MPC8540 1 /* MPC8540 specific */ 42 #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ 43 44 /* 45 * default CCARBAR is at 0xff700000 46 * assume U-Boot is less than 0.5MB 47 */ 48 #define CONFIG_SYS_TEXT_BASE 0xfff80000 49 50 #ifndef CONFIG_HAS_FEC 51 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 52 #endif 53 54 #define CONFIG_PCI 55 #define CONFIG_PCI_INDIRECT_BRIDGE 56 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 57 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 58 #define CONFIG_ENV_OVERWRITE 59 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 60 61 /* 62 * sysclk for MPC85xx 63 * 64 * Two valid values are: 65 * 33000000 66 * 66000000 67 * 68 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 69 * is likely the desired value here, so that is now the default. 70 * The board, however, can run at 66MHz. In any event, this value 71 * must match the settings of some switches. Details can be found 72 * in the README.mpc85xxads. 73 * 74 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 75 * 33MHz to accommodate, based on a PCI pin. 76 * Note that PCI-X won't work at 33MHz. 77 */ 78 79 #ifndef CONFIG_SYS_CLK_FREQ 80 #define CONFIG_SYS_CLK_FREQ 33000000 81 #endif 82 83 84 /* 85 * These can be toggled for performance analysis, otherwise use default. 86 */ 87 #define CONFIG_L2_CACHE /* toggle L2 cache */ 88 #define CONFIG_BTB /* toggle branch predition */ 89 90 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 91 #define CONFIG_SYS_MEMTEST_END 0x00400000 92 93 #define CONFIG_SYS_CCSRBAR 0xe0000000 94 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 95 96 /* DDR Setup */ 97 #define CONFIG_FSL_DDR1 98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 99 #define CONFIG_DDR_SPD 100 #undef CONFIG_FSL_DDR_INTERACTIVE 101 102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 103 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 114 /* These are used when DDR doesn't use SPD. */ 115 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 117 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 118 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 119 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 120 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 121 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 122 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 123 124 /* 125 * SDRAM on the Local Bus 126 */ 127 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 128 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 129 130 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 131 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 132 133 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 135 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 136 #undef CONFIG_SYS_FLASH_CHECKSUM 137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 139 140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 141 142 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 143 #define CONFIG_SYS_RAMBOOT 144 #else 145 #undef CONFIG_SYS_RAMBOOT 146 #endif 147 148 #define CONFIG_FLASH_CFI_DRIVER 149 #define CONFIG_SYS_FLASH_CFI 150 #define CONFIG_SYS_FLASH_EMPTY_INFO 151 152 #undef CONFIG_CLOCKS_IN_MHZ 153 154 155 /* 156 * Local Bus Definitions 157 */ 158 159 /* 160 * Base Register 2 and Option Register 2 configure SDRAM. 161 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 162 * 163 * For BR2, need: 164 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 165 * port-size = 32-bits = BR2[19:20] = 11 166 * no parity checking = BR2[21:22] = 00 167 * SDRAM for MSEL = BR2[24:26] = 011 168 * Valid = BR[31] = 1 169 * 170 * 0 4 8 12 16 20 24 28 171 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 172 * 173 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 174 * FIXME: the top 17 bits of BR2. 175 */ 176 177 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 178 179 /* 180 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 181 * 182 * For OR2, need: 183 * 64MB mask for AM, OR2[0:7] = 1111 1100 184 * XAM, OR2[17:18] = 11 185 * 9 columns OR2[19-21] = 010 186 * 13 rows OR2[23-25] = 100 187 * EAD set for extra time OR[31] = 1 188 * 189 * 0 4 8 12 16 20 24 28 190 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 191 */ 192 193 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 194 195 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 196 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 197 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 198 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 199 200 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 201 | LSDMR_RFCR5 \ 202 | LSDMR_PRETOACT3 \ 203 | LSDMR_ACTTORW3 \ 204 | LSDMR_BL8 \ 205 | LSDMR_WRC2 \ 206 | LSDMR_CL3 \ 207 | LSDMR_RFEN \ 208 ) 209 210 /* 211 * SDRAM Controller configuration sequence. 212 */ 213 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 214 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 215 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 216 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 217 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 218 219 220 /* 221 * 32KB, 8-bit wide for ADS config reg 222 */ 223 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 224 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 225 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 226 227 #define CONFIG_SYS_INIT_RAM_LOCK 1 228 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 230 231 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 232 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 233 234 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 235 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 236 237 /* Serial Port */ 238 #define CONFIG_CONS_INDEX 1 239 #define CONFIG_SYS_NS16550 240 #define CONFIG_SYS_NS16550_SERIAL 241 #define CONFIG_SYS_NS16550_REG_SIZE 1 242 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 243 244 #define CONFIG_SYS_BAUDRATE_TABLE \ 245 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 246 247 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 248 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 249 250 /* Use the HUSH parser */ 251 #define CONFIG_SYS_HUSH_PARSER 252 #ifdef CONFIG_SYS_HUSH_PARSER 253 #endif 254 255 /* pass open firmware flat tree */ 256 #define CONFIG_OF_LIBFDT 1 257 #define CONFIG_OF_BOARD_SETUP 1 258 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 259 260 /* 261 * I2C 262 */ 263 #define CONFIG_SYS_I2C 264 #define CONFIG_SYS_I2C_FSL 265 #define CONFIG_SYS_FSL_I2C_SPEED 400000 266 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 267 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 268 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 269 270 /* RapidIO MMU */ 271 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 272 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 273 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 274 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 275 276 /* 277 * General PCI 278 * Memory space is mapped 1-1, but I/O space must start from 0. 279 */ 280 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 281 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 282 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 283 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 284 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 285 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 286 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 287 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 288 289 #if defined(CONFIG_PCI) 290 291 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 292 293 #undef CONFIG_EEPRO100 294 #undef CONFIG_TULIP 295 296 #if !defined(CONFIG_PCI_PNP) 297 #define PCI_ENET0_IOADDR 0xe0000000 298 #define PCI_ENET0_MEMADDR 0xe0000000 299 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 300 #endif 301 302 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 303 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 304 305 #endif /* CONFIG_PCI */ 306 307 308 #if defined(CONFIG_TSEC_ENET) 309 310 #define CONFIG_MII 1 /* MII PHY management */ 311 #define CONFIG_TSEC1 1 312 #define CONFIG_TSEC1_NAME "TSEC0" 313 #define CONFIG_TSEC2 1 314 #define CONFIG_TSEC2_NAME "TSEC1" 315 #define TSEC1_PHY_ADDR 0 316 #define TSEC2_PHY_ADDR 1 317 #define TSEC1_PHYIDX 0 318 #define TSEC2_PHYIDX 0 319 #define TSEC1_FLAGS TSEC_GIGABIT 320 #define TSEC2_FLAGS TSEC_GIGABIT 321 322 323 #if CONFIG_HAS_FEC 324 #define CONFIG_MPC85XX_FEC 1 325 #define CONFIG_MPC85XX_FEC_NAME "FEC" 326 #define FEC_PHY_ADDR 3 327 #define FEC_PHYIDX 0 328 #define FEC_FLAGS 0 329 #endif 330 331 /* Options are: TSEC[0-1], FEC */ 332 #define CONFIG_ETHPRIME "TSEC0" 333 334 #endif /* CONFIG_TSEC_ENET */ 335 336 337 /* 338 * Environment 339 */ 340 #ifndef CONFIG_SYS_RAMBOOT 341 #define CONFIG_ENV_IS_IN_FLASH 1 342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 343 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 344 #define CONFIG_ENV_SIZE 0x2000 345 #else 346 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 347 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 348 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 349 #define CONFIG_ENV_SIZE 0x2000 350 #endif 351 352 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 353 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 354 355 356 /* 357 * BOOTP options 358 */ 359 #define CONFIG_BOOTP_BOOTFILESIZE 360 #define CONFIG_BOOTP_BOOTPATH 361 #define CONFIG_BOOTP_GATEWAY 362 #define CONFIG_BOOTP_HOSTNAME 363 364 365 /* 366 * Command line configuration. 367 */ 368 #include <config_cmd_default.h> 369 370 #define CONFIG_CMD_PING 371 #define CONFIG_CMD_I2C 372 #define CONFIG_CMD_ELF 373 #define CONFIG_CMD_IRQ 374 #define CONFIG_CMD_SETEXPR 375 376 #if defined(CONFIG_PCI) 377 #define CONFIG_CMD_PCI 378 #endif 379 380 #if defined(CONFIG_SYS_RAMBOOT) 381 #undef CONFIG_CMD_SAVEENV 382 #undef CONFIG_CMD_LOADS 383 #endif 384 385 386 #undef CONFIG_WATCHDOG /* watchdog disabled */ 387 388 /* 389 * Miscellaneous configurable options 390 */ 391 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 392 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 393 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 394 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 395 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 396 397 #if defined(CONFIG_CMD_KGDB) 398 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 399 #else 400 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 401 #endif 402 403 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 404 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 405 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 406 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 407 408 /* 409 * For booting Linux, the board info and command line data 410 * have to be in the first 64 MB of memory, since this is 411 * the maximum mapped by the Linux kernel during initialization. 412 */ 413 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 414 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 415 416 #if defined(CONFIG_CMD_KGDB) 417 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 418 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 419 #endif 420 421 422 /* 423 * Environment Configuration 424 */ 425 426 /* The mac addresses for all ethernet interface */ 427 #if defined(CONFIG_TSEC_ENET) 428 #define CONFIG_HAS_ETH0 429 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD 430 #define CONFIG_HAS_ETH1 431 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 432 #define CONFIG_HAS_ETH2 433 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 434 #endif 435 436 #define CONFIG_IPADDR 192.168.1.253 437 438 #define CONFIG_HOSTNAME unknown 439 #define CONFIG_ROOTPATH "/nfsroot" 440 #define CONFIG_BOOTFILE "your.uImage" 441 442 #define CONFIG_SERVERIP 192.168.1.1 443 #define CONFIG_GATEWAYIP 192.168.1.1 444 #define CONFIG_NETMASK 255.255.255.0 445 446 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 447 448 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 449 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 450 451 #define CONFIG_BAUDRATE 115200 452 453 #define CONFIG_EXTRA_ENV_SETTINGS \ 454 "netdev=eth0\0" \ 455 "consoledev=ttyS0\0" \ 456 "ramdiskaddr=1000000\0" \ 457 "ramdiskfile=your.ramdisk.u-boot\0" \ 458 "fdtaddr=400000\0" \ 459 "fdtfile=your.fdt.dtb\0" 460 461 #define CONFIG_NFSBOOTCOMMAND \ 462 "setenv bootargs root=/dev/nfs rw " \ 463 "nfsroot=$serverip:$rootpath " \ 464 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 465 "console=$consoledev,$baudrate $othbootargs;" \ 466 "tftp $loadaddr $bootfile;" \ 467 "tftp $fdtaddr $fdtfile;" \ 468 "bootm $loadaddr - $fdtaddr" 469 470 #define CONFIG_RAMBOOTCOMMAND \ 471 "setenv bootargs root=/dev/ram rw " \ 472 "console=$consoledev,$baudrate $othbootargs;" \ 473 "tftp $ramdiskaddr $ramdiskfile;" \ 474 "tftp $loadaddr $bootfile;" \ 475 "tftp $fdtaddr $fdtfile;" \ 476 "bootm $loadaddr $ramdiskaddr $fdtaddr" 477 478 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 479 480 #endif /* __CONFIG_H */ 481