1 /* 2 * (C) Copyright 2006-2010 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mpc8349emds board configuration file 26 * 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_E300 1 /* E300 Family */ 36 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 37 #define CONFIG_MPC834x 1 /* MPC834x family */ 38 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 39 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ 40 41 #define CONFIG_SYS_TEXT_BASE 0xFE000000 42 43 #define CONFIG_PCI_66M 44 #ifdef CONFIG_PCI_66M 45 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 46 #else 47 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 48 #endif 49 50 #ifdef CONFIG_PCISLAVE 51 #define CONFIG_PCI 52 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ 53 #endif /* CONFIG_PCISLAVE */ 54 55 #ifndef CONFIG_SYS_CLK_FREQ 56 #ifdef CONFIG_PCI_66M 57 #define CONFIG_SYS_CLK_FREQ 66000000 58 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 59 #else 60 #define CONFIG_SYS_CLK_FREQ 33000000 61 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 62 #endif 63 #endif 64 65 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 66 67 #define CONFIG_SYS_IMMR 0xE0000000 68 69 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 70 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 71 #define CONFIG_SYS_MEMTEST_END 0x00100000 72 73 /* 74 * DDR Setup 75 */ 76 #define CONFIG_DDR_ECC /* support DDR ECC function */ 77 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 78 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 79 80 /* 81 * 32-bit data path mode. 82 * 83 * Please note that using this mode for devices with the real density of 64-bit 84 * effectively reduces the amount of available memory due to the effect of 85 * wrapping around while translating address to row/columns, for example in the 86 * 256MB module the upper 128MB get aliased with contents of the lower 87 * 128MB); normally this define should be used for devices with real 32-bit 88 * data path. 89 */ 90 #undef CONFIG_DDR_32BIT 91 92 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 94 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 96 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 97 #undef CONFIG_DDR_2T_TIMING 98 99 /* 100 * DDRCDR - DDR Control Driver Register 101 */ 102 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 103 104 #if defined(CONFIG_SPD_EEPROM) 105 /* 106 * Determine DDR configuration from I2C interface. 107 */ 108 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ 109 #else 110 /* 111 * Manually set up DDR parameters 112 */ 113 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 114 #if defined(CONFIG_DDR_II) 115 #define CONFIG_SYS_DDRCDR 0x80080001 116 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f 117 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 118 #define CONFIG_SYS_DDR_TIMING_0 0x00220802 119 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 120 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 122 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 123 #define CONFIG_SYS_DDR_MODE 0x47d00432 124 #define CONFIG_SYS_DDR_MODE2 0x8000c000 125 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 126 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 127 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 128 #else 129 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 130 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 131 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 132 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 133 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ 134 135 #if defined(CONFIG_DDR_32BIT) 136 /* set burst length to 8 for 32-bit data path */ 137 #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ 138 #else 139 /* the default burst length is 4 - for 64-bit data path */ 140 #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ 141 #endif 142 #endif 143 #endif 144 145 /* 146 * SDRAM on the Local Bus 147 */ 148 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ 149 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 150 151 /* 152 * FLASH on the Local Bus 153 */ 154 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 155 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 156 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 157 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ 158 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 159 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 160 161 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 162 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 163 BR_V) /* valid */ 164 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 165 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 166 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 167 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 168 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ 169 170 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 171 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 172 173 #undef CONFIG_SYS_FLASH_CHECKSUM 174 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 175 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 176 177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 178 179 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 180 #define CONFIG_SYS_RAMBOOT 181 #else 182 #undef CONFIG_SYS_RAMBOOT 183 #endif 184 185 /* 186 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg 187 */ 188 #define CONFIG_SYS_BCSR 0xE2400000 189 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ 190 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 191 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ 192 #define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ 193 194 #define CONFIG_SYS_INIT_RAM_LOCK 1 195 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 196 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 197 198 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 201 202 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 203 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 204 205 /* 206 * Local Bus LCRR and LBCR regs 207 * LCRR: DLL bypass, Clock divider is 4 208 * External Local Bus rate is 209 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 210 */ 211 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 212 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 213 #define CONFIG_SYS_LBC_LBCR 0x00000000 214 215 /* 216 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. 217 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM 218 */ 219 #undef CONFIG_SYS_LB_SDRAM 220 221 #ifdef CONFIG_SYS_LB_SDRAM 222 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ 223 /* 224 * Base Register 2 and Option Register 2 configure SDRAM. 225 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 226 * 227 * For BR2, need: 228 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 229 * port-size = 32-bits = BR2[19:20] = 11 230 * no parity checking = BR2[21:22] = 00 231 * SDRAM for MSEL = BR2[24:26] = 011 232 * Valid = BR[31] = 1 233 * 234 * 0 4 8 12 16 20 24 28 235 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 236 * 237 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 238 * FIXME: the top 17 bits of BR2. 239 */ 240 241 #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ 242 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 243 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ 244 245 /* 246 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 247 * 248 * For OR2, need: 249 * 64MB mask for AM, OR2[0:7] = 1111 1100 250 * XAM, OR2[17:18] = 11 251 * 9 columns OR2[19-21] = 010 252 * 13 rows OR2[23-25] = 100 253 * EAD set for extra time OR[31] = 1 254 * 255 * 0 4 8 12 16 20 24 28 256 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 257 */ 258 259 #define CONFIG_SYS_OR2_PRELIM 0xFC006901 260 261 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 262 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ 263 264 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ 265 | LSDMR_BSMA1516 \ 266 | LSDMR_RFCR8 \ 267 | LSDMR_PRETOACT6 \ 268 | LSDMR_ACTTORW3 \ 269 | LSDMR_BL8 \ 270 | LSDMR_WRC3 \ 271 | LSDMR_CL3 \ 272 ) 273 274 /* 275 * SDRAM Controller configuration sequence. 276 */ 277 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 278 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 279 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 280 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 281 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 282 #endif 283 284 /* 285 * Serial Port 286 */ 287 #define CONFIG_CONS_INDEX 1 288 #define CONFIG_SYS_NS16550 289 #define CONFIG_SYS_NS16550_SERIAL 290 #define CONFIG_SYS_NS16550_REG_SIZE 1 291 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 292 293 #define CONFIG_SYS_BAUDRATE_TABLE \ 294 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 295 296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 298 299 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 300 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 301 /* Use the HUSH parser */ 302 #define CONFIG_SYS_HUSH_PARSER 303 #ifdef CONFIG_SYS_HUSH_PARSER 304 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 305 #endif 306 307 /* pass open firmware flat tree */ 308 #define CONFIG_OF_LIBFDT 1 309 #define CONFIG_OF_BOARD_SETUP 1 310 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 311 312 /* I2C */ 313 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 314 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 315 #define CONFIG_FSL_I2C 316 #define CONFIG_I2C_MULTI_BUS 317 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 318 #define CONFIG_SYS_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 320 #define CONFIG_SYS_I2C_OFFSET 0x3000 321 #define CONFIG_SYS_I2C2_OFFSET 0x3100 322 323 /* SPI */ 324 #define CONFIG_MPC8XXX_SPI 325 #undef CONFIG_SOFT_SPI /* SPI bit-banged */ 326 327 /* GPIOs. Used as SPI chip selects */ 328 #define CONFIG_SYS_GPIO1_PRELIM 329 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ 330 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ 331 332 /* TSEC */ 333 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 334 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 335 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 336 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 337 338 /* USB */ 339 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ 340 341 /* 342 * General PCI 343 * Addresses are mapped 1-1. 344 */ 345 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 346 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 347 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 348 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 349 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 350 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 351 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 352 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 353 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 354 355 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 356 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 357 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 358 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 359 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 360 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 361 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 362 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 363 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 364 365 #if defined(CONFIG_PCI) 366 367 #define PCI_ONE_PCI1 368 #if defined(PCI_64BIT) 369 #undef PCI_ALL_PCI1 370 #undef PCI_TWO_PCI1 371 #undef PCI_ONE_PCI1 372 #endif 373 374 #define CONFIG_NET_MULTI 375 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 376 #define CONFIG_83XX_PCI_STREAMING 377 378 #undef CONFIG_EEPRO100 379 #undef CONFIG_TULIP 380 381 #if !defined(CONFIG_PCI_PNP) 382 #define PCI_ENET0_IOADDR 0xFIXME 383 #define PCI_ENET0_MEMADDR 0xFIXME 384 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 385 #endif 386 387 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 388 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 389 390 #endif /* CONFIG_PCI */ 391 392 /* 393 * TSEC configuration 394 */ 395 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 396 397 #if defined(CONFIG_TSEC_ENET) 398 #ifndef CONFIG_NET_MULTI 399 #define CONFIG_NET_MULTI 1 400 #endif 401 402 #define CONFIG_GMII 1 /* MII PHY management */ 403 #define CONFIG_TSEC1 1 404 #define CONFIG_TSEC1_NAME "TSEC0" 405 #define CONFIG_TSEC2 1 406 #define CONFIG_TSEC2_NAME "TSEC1" 407 #define TSEC1_PHY_ADDR 0 408 #define TSEC2_PHY_ADDR 1 409 #define TSEC1_PHYIDX 0 410 #define TSEC2_PHYIDX 0 411 #define TSEC1_FLAGS TSEC_GIGABIT 412 #define TSEC2_FLAGS TSEC_GIGABIT 413 414 /* Options are: TSEC[0-1] */ 415 #define CONFIG_ETHPRIME "TSEC0" 416 417 #endif /* CONFIG_TSEC_ENET */ 418 419 /* 420 * Configure on-board RTC 421 */ 422 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 423 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 424 425 /* 426 * Environment 427 */ 428 #ifndef CONFIG_SYS_RAMBOOT 429 #define CONFIG_ENV_IS_IN_FLASH 1 430 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 431 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 432 #define CONFIG_ENV_SIZE 0x2000 433 434 /* Address and size of Redundant Environment Sector */ 435 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 436 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 437 438 #else 439 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 440 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 441 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 442 #define CONFIG_ENV_SIZE 0x2000 443 #endif 444 445 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 446 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 447 448 449 /* 450 * BOOTP options 451 */ 452 #define CONFIG_BOOTP_BOOTFILESIZE 453 #define CONFIG_BOOTP_BOOTPATH 454 #define CONFIG_BOOTP_GATEWAY 455 #define CONFIG_BOOTP_HOSTNAME 456 457 458 /* 459 * Command line configuration. 460 */ 461 #include <config_cmd_default.h> 462 463 #define CONFIG_CMD_PING 464 #define CONFIG_CMD_I2C 465 #define CONFIG_CMD_DATE 466 #define CONFIG_CMD_MII 467 468 #if defined(CONFIG_PCI) 469 #define CONFIG_CMD_PCI 470 #endif 471 472 #if defined(CONFIG_SYS_RAMBOOT) 473 #undef CONFIG_CMD_SAVEENV 474 #undef CONFIG_CMD_LOADS 475 #endif 476 477 478 #undef CONFIG_WATCHDOG /* watchdog disabled */ 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 484 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 485 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 486 487 #if defined(CONFIG_CMD_KGDB) 488 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 489 #else 490 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 491 #endif 492 493 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 494 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 495 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 496 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 497 498 /* 499 * For booting Linux, the board info and command line data 500 * have to be in the first 256 MB of memory, since this is 501 * the maximum mapped by the Linux kernel during initialization. 502 */ 503 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 504 505 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 506 507 #if 1 /*528/264*/ 508 #define CONFIG_SYS_HRCW_LOW (\ 509 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 510 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 511 HRCWL_CSB_TO_CLKIN |\ 512 HRCWL_VCO_1X2 |\ 513 HRCWL_CORE_TO_CSB_2X1) 514 #elif 0 /*396/132*/ 515 #define CONFIG_SYS_HRCW_LOW (\ 516 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 517 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 518 HRCWL_CSB_TO_CLKIN |\ 519 HRCWL_VCO_1X4 |\ 520 HRCWL_CORE_TO_CSB_3X1) 521 #elif 0 /*264/132*/ 522 #define CONFIG_SYS_HRCW_LOW (\ 523 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 524 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 525 HRCWL_CSB_TO_CLKIN |\ 526 HRCWL_VCO_1X4 |\ 527 HRCWL_CORE_TO_CSB_2X1) 528 #elif 0 /*132/132*/ 529 #define CONFIG_SYS_HRCW_LOW (\ 530 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 531 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 532 HRCWL_CSB_TO_CLKIN |\ 533 HRCWL_VCO_1X4 |\ 534 HRCWL_CORE_TO_CSB_1X1) 535 #elif 0 /*264/264 */ 536 #define CONFIG_SYS_HRCW_LOW (\ 537 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 538 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 539 HRCWL_CSB_TO_CLKIN |\ 540 HRCWL_VCO_1X4 |\ 541 HRCWL_CORE_TO_CSB_1X1) 542 #endif 543 544 #ifdef CONFIG_PCISLAVE 545 #define CONFIG_SYS_HRCW_HIGH (\ 546 HRCWH_PCI_AGENT |\ 547 HRCWH_64_BIT_PCI |\ 548 HRCWH_PCI1_ARBITER_DISABLE |\ 549 HRCWH_PCI2_ARBITER_DISABLE |\ 550 HRCWH_CORE_ENABLE |\ 551 HRCWH_FROM_0X00000100 |\ 552 HRCWH_BOOTSEQ_DISABLE |\ 553 HRCWH_SW_WATCHDOG_DISABLE |\ 554 HRCWH_ROM_LOC_LOCAL_16BIT |\ 555 HRCWH_TSEC1M_IN_GMII |\ 556 HRCWH_TSEC2M_IN_GMII ) 557 #else 558 #if defined(PCI_64BIT) 559 #define CONFIG_SYS_HRCW_HIGH (\ 560 HRCWH_PCI_HOST |\ 561 HRCWH_64_BIT_PCI |\ 562 HRCWH_PCI1_ARBITER_ENABLE |\ 563 HRCWH_PCI2_ARBITER_DISABLE |\ 564 HRCWH_CORE_ENABLE |\ 565 HRCWH_FROM_0X00000100 |\ 566 HRCWH_BOOTSEQ_DISABLE |\ 567 HRCWH_SW_WATCHDOG_DISABLE |\ 568 HRCWH_ROM_LOC_LOCAL_16BIT |\ 569 HRCWH_TSEC1M_IN_GMII |\ 570 HRCWH_TSEC2M_IN_GMII ) 571 #else 572 #define CONFIG_SYS_HRCW_HIGH (\ 573 HRCWH_PCI_HOST |\ 574 HRCWH_32_BIT_PCI |\ 575 HRCWH_PCI1_ARBITER_ENABLE |\ 576 HRCWH_PCI2_ARBITER_ENABLE |\ 577 HRCWH_CORE_ENABLE |\ 578 HRCWH_FROM_0X00000100 |\ 579 HRCWH_BOOTSEQ_DISABLE |\ 580 HRCWH_SW_WATCHDOG_DISABLE |\ 581 HRCWH_ROM_LOC_LOCAL_16BIT |\ 582 HRCWH_TSEC1M_IN_GMII |\ 583 HRCWH_TSEC2M_IN_GMII ) 584 #endif /* PCI_64BIT */ 585 #endif /* CONFIG_PCISLAVE */ 586 587 /* 588 * System performance 589 */ 590 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 591 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 592 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 593 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 594 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 595 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 596 597 /* System IO Config */ 598 #define CONFIG_SYS_SICRH 0 599 #define CONFIG_SYS_SICRL SICRL_LDP_A 600 601 #define CONFIG_SYS_HID0_INIT 0x000000000 602 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 603 HID0_ENABLE_INSTRUCTION_CACHE) 604 605 /* #define CONFIG_SYS_HID0_FINAL (\ 606 HID0_ENABLE_INSTRUCTION_CACHE |\ 607 HID0_ENABLE_M_BIT |\ 608 HID0_ENABLE_ADDRESS_BROADCAST ) */ 609 610 611 #define CONFIG_SYS_HID2 HID2_HBE 612 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 613 614 /* DDR @ 0x00000000 */ 615 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 616 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 617 618 /* PCI @ 0x80000000 */ 619 #ifdef CONFIG_PCI 620 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 621 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 622 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 623 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 624 #else 625 #define CONFIG_SYS_IBAT1L (0) 626 #define CONFIG_SYS_IBAT1U (0) 627 #define CONFIG_SYS_IBAT2L (0) 628 #define CONFIG_SYS_IBAT2U (0) 629 #endif 630 631 #ifdef CONFIG_MPC83XX_PCI2 632 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 633 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 634 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 635 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 636 #else 637 #define CONFIG_SYS_IBAT3L (0) 638 #define CONFIG_SYS_IBAT3U (0) 639 #define CONFIG_SYS_IBAT4L (0) 640 #define CONFIG_SYS_IBAT4U (0) 641 #endif 642 643 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 644 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 645 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 646 647 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 648 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 649 BATL_GUARDEDSTORAGE) 650 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 651 652 #define CONFIG_SYS_IBAT7L (0) 653 #define CONFIG_SYS_IBAT7U (0) 654 655 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 656 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 657 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 658 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 659 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 660 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 661 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 662 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 663 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 664 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 665 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 666 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 667 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 668 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 669 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 670 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 671 672 /* 673 * Internal Definitions 674 * 675 * Boot Flags 676 */ 677 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 678 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 679 680 #if defined(CONFIG_CMD_KGDB) 681 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 682 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 683 #endif 684 685 /* 686 * Environment Configuration 687 */ 688 #define CONFIG_ENV_OVERWRITE 689 690 #if defined(CONFIG_TSEC_ENET) 691 #define CONFIG_HAS_ETH1 692 #define CONFIG_HAS_ETH0 693 #endif 694 695 #define CONFIG_HOSTNAME mpc8349emds 696 #define CONFIG_ROOTPATH /nfsroot/rootfs 697 #define CONFIG_BOOTFILE uImage 698 699 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 700 701 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 702 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 703 704 #define CONFIG_BAUDRATE 115200 705 706 #define CONFIG_PREBOOT "echo;" \ 707 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 708 "echo" 709 710 #define CONFIG_EXTRA_ENV_SETTINGS \ 711 "netdev=eth0\0" \ 712 "hostname=mpc8349emds\0" \ 713 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 714 "nfsroot=${serverip}:${rootpath}\0" \ 715 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 716 "addip=setenv bootargs ${bootargs} " \ 717 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 718 ":${hostname}:${netdev}:off panic=1\0" \ 719 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 720 "flash_nfs=run nfsargs addip addtty;" \ 721 "bootm ${kernel_addr}\0" \ 722 "flash_self=run ramargs addip addtty;" \ 723 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 724 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 725 "bootm\0" \ 726 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ 727 "update=protect off fe000000 fe03ffff; " \ 728 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ 729 "upd=run load update\0" \ 730 "fdtaddr=780000\0" \ 731 "fdtfile=mpc834x_mds.dtb\0" \ 732 "" 733 734 #define CONFIG_NFSBOOTCOMMAND \ 735 "setenv bootargs root=/dev/nfs rw " \ 736 "nfsroot=$serverip:$rootpath " \ 737 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 738 "console=$consoledev,$baudrate $othbootargs;" \ 739 "tftp $loadaddr $bootfile;" \ 740 "tftp $fdtaddr $fdtfile;" \ 741 "bootm $loadaddr - $fdtaddr" 742 743 #define CONFIG_RAMBOOTCOMMAND \ 744 "setenv bootargs root=/dev/ram rw " \ 745 "console=$consoledev,$baudrate $othbootargs;" \ 746 "tftp $ramdiskaddr $ramdiskfile;" \ 747 "tftp $loadaddr $bootfile;" \ 748 "tftp $fdtaddr $fdtfile;" \ 749 "bootm $loadaddr $ramdiskaddr $fdtaddr" 750 751 #define CONFIG_BOOTCOMMAND "run flash_self" 752 753 #endif /* __CONFIG_H */ 754