1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_C29XPCIE 17 #define CONFIG_PPC_C29X 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 22 #define CONFIG_SYS_TEXT_BASE 0x11000000 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 24 #endif 25 26 #ifndef CONFIG_SYS_TEXT_BASE 27 #define CONFIG_SYS_TEXT_BASE 0xeff80000 28 #endif 29 30 #ifndef CONFIG_RESET_VECTOR_ADDRESS 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 32 #endif 33 34 #ifndef CONFIG_SYS_MONITOR_BASE 35 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 36 #endif 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE /* BOOKE */ 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_MPC85xx 42 #define CONFIG_FSL_IFC /* Enable IFC Support */ 43 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 44 45 #define CONFIG_PCI /* Enable PCI/PCIE */ 46 #ifdef CONFIG_PCI 47 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 49 #define CONFIG_PCI_INDIRECT_BRIDGE 50 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 51 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 52 53 #define CONFIG_CMD_NET 54 #define CONFIG_CMD_PCI 55 56 #define CONFIG_E1000 57 58 /* 59 * PCI Windows 60 * Memory space is mapped 1-1, but I/O space must start from 0. 61 */ 62 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 63 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 64 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 65 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 66 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 67 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 68 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 69 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 70 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 71 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 72 73 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 74 75 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 76 #define CONFIG_DOS_PARTITION 77 #endif 78 79 #define CONFIG_FSL_LAW /* Use common FSL init code */ 80 #define CONFIG_TSEC_ENET 81 #define CONFIG_ENV_OVERWRITE 82 83 #define CONFIG_DDR_CLK_FREQ 100000000 84 #define CONFIG_SYS_CLK_FREQ 66666666 85 86 #define CONFIG_HWCONFIG 87 88 /* 89 * These can be toggled for performance analysis, otherwise use default. 90 */ 91 #define CONFIG_L2_CACHE /* toggle L2 cache */ 92 #define CONFIG_BTB /* toggle branch predition */ 93 94 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 95 96 #define CONFIG_ENABLE_36BIT_PHYS 97 98 #define CONFIG_ADDR_MAP 1 99 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 100 101 #define CONFIG_SYS_MEMTEST_START 0x00200000 102 #define CONFIG_SYS_MEMTEST_END 0x00400000 103 #define CONFIG_PANIC_HANG 104 105 /* DDR Setup */ 106 #define CONFIG_FSL_DDR3 107 #define CONFIG_DDR_SPD 108 #define CONFIG_SYS_SPD_BUS_NUM 0 109 #define SPD_EEPROM_ADDRESS 0x50 110 #define CONFIG_SYS_DDR_RAW_TIMING 111 112 /* DDR ECC Setup*/ 113 #define CONFIG_DDR_ECC 114 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 116 117 #define CONFIG_SYS_SDRAM_SIZE 512 118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 120 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 123 124 #define CONFIG_SYS_CCSRBAR 0xffe00000 125 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 126 127 /* Platform SRAM setting */ 128 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 129 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 130 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 131 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 132 133 /* 134 * IFC Definitions 135 */ 136 /* NOR Flash on IFC */ 137 #define CONFIG_SYS_FLASH_BASE 0xec000000 138 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 139 140 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 141 142 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 143 #define CONFIG_SYS_MAX_FLASH_BANKS 1 144 145 #define CONFIG_SYS_FLASH_QUIET_TEST 146 #define CONFIG_FLASH_SHOW_PROGRESS 45 147 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 148 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 149 150 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 151 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 152 CSPR_PORT_SIZE_16 | \ 153 CSPR_MSEL_NOR | \ 154 CSPR_V) 155 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 156 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 157 158 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 159 FTIM0_NOR_TEADC(0x5) | \ 160 FTIM0_NOR_TEAHC(0x5)) 161 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 162 FTIM1_NOR_TRAD_NOR(0x1A) |\ 163 FTIM1_NOR_TSEQRAD_NOR(0x13)) 164 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 165 FTIM2_NOR_TCH(0x4) | \ 166 FTIM2_NOR_TWPH(0x0E) | \ 167 FTIM2_NOR_TWP(0x1c)) 168 #define CONFIG_SYS_NOR_FTIM3 0x0 169 170 /* CFI for NOR Flash */ 171 #define CONFIG_FLASH_CFI_DRIVER 172 #define CONFIG_SYS_FLASH_CFI 173 #define CONFIG_SYS_FLASH_EMPTY_INFO 174 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 175 176 /* NAND Flash on IFC */ 177 #define CONFIG_NAND_FSL_IFC 178 #define CONFIG_SYS_NAND_BASE 0xff800000 179 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 180 181 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 182 183 #define CONFIG_SYS_MAX_NAND_DEVICE 1 184 #define CONFIG_MTD_NAND_VERIFY_WRITE 185 #define CONFIG_CMD_NAND 186 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 187 188 /* 8Bit NAND Flash - K9F1G08U0B */ 189 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 190 | CSPR_PORT_SIZE_8 \ 191 | CSPR_MSEL_NAND \ 192 | CSPR_V) 193 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 194 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 195 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 196 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 197 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 198 | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ 199 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 200 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 201 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 202 FTIM0_NAND_TWP(0x0c) | \ 203 FTIM0_NAND_TWCHT(0x08) | \ 204 FTIM0_NAND_TWH(0x06)) 205 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 206 FTIM1_NAND_TWBE(0x1d) | \ 207 FTIM1_NAND_TRR(0x08) | \ 208 FTIM1_NAND_TRP(0x0c)) 209 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 210 FTIM2_NAND_TREH(0x0a) | \ 211 FTIM2_NAND_TWHRE(0x18)) 212 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 213 214 #define CONFIG_SYS_NAND_DDR_LAW 11 215 216 /* Set up IFC registers for boot location NOR/NAND */ 217 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 224 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 225 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 226 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 227 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 228 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 229 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 230 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 231 232 /* CPLD on IFC, selected by CS2 */ 233 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 234 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 235 | CONFIG_SYS_CPLD_BASE) 236 237 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 238 | CSPR_PORT_SIZE_8 \ 239 | CSPR_MSEL_GPCM \ 240 | CSPR_V) 241 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 242 #define CONFIG_SYS_CSOR2 0x0 243 /* CPLD Timing parameters for IFC CS2 */ 244 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 245 FTIM0_GPCM_TEADC(0x0e) | \ 246 FTIM0_GPCM_TEAHC(0x0e)) 247 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 248 FTIM1_GPCM_TRAD(0x1f)) 249 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 250 FTIM2_GPCM_TCH(0x0) | \ 251 FTIM2_GPCM_TWP(0x1f)) 252 #define CONFIG_SYS_CS2_FTIM3 0x0 253 254 #if defined(CONFIG_RAMBOOT_SPIFLASH) 255 #define CONFIG_SYS_RAMBOOT 256 #define CONFIG_SYS_EXTRA_ENV_RELOC 257 #endif 258 259 #define CONFIG_BOARD_EARLY_INIT_R 260 261 #define CONFIG_SYS_INIT_RAM_LOCK 262 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 263 #define CONFIG_SYS_INIT_RAM_END 0x00004000 264 265 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 266 - GENERATED_GBL_DATA_SIZE) 267 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 268 269 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 270 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 271 272 /* Serial Port */ 273 #define CONFIG_CONS_INDEX 1 274 #define CONFIG_SYS_NS16550 275 #define CONFIG_SYS_NS16550_SERIAL 276 #define CONFIG_SYS_NS16550_REG_SIZE 1 277 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 278 279 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 280 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 281 282 #define CONFIG_SYS_BAUDRATE_TABLE \ 283 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 284 285 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 286 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 287 288 /* Use the HUSH parser */ 289 #define CONFIG_SYS_HUSH_PARSER 290 291 /* 292 * Pass open firmware flat tree 293 */ 294 #define CONFIG_OF_LIBFDT 295 #define CONFIG_OF_BOARD_SETUP 296 #define CONFIG_OF_STDOUT_VIA_ALIAS 297 298 /* new uImage format support */ 299 #define CONFIG_FIT 300 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 301 302 #define CONFIG_SYS_I2C 303 #define CONFIG_SYS_I2C_FSL 304 #define CONFIG_SYS_FSL_I2C_SPEED 400000 305 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 306 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 307 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 308 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 309 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 310 311 /* I2C EEPROM */ 312 /* enable read and write access to EEPROM */ 313 #define CONFIG_CMD_EEPROM 314 #define CONFIG_SYS_I2C_MULTI_EEPROMS 315 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 316 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 317 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 318 319 #define CONFIG_CMD_I2C 320 321 /* eSPI - Enhanced SPI */ 322 #define CONFIG_FSL_ESPI 323 #define CONFIG_SPI_FLASH 324 #define CONFIG_SPI_FLASH_SPANSION 325 #define CONFIG_SPI_FLASH_EON 326 #define CONFIG_CMD_SF 327 #define CONFIG_SF_DEFAULT_SPEED 10000000 328 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 329 330 #ifdef CONFIG_TSEC_ENET 331 #define CONFIG_NET_MULTI 332 #define CONFIG_MII /* MII PHY management */ 333 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 334 #define CONFIG_TSEC1 1 335 #define CONFIG_TSEC1_NAME "eTSEC1" 336 #define CONFIG_TSEC2 1 337 #define CONFIG_TSEC2_NAME "eTSEC2" 338 339 /* Default mode is RGMII mode */ 340 #define TSEC1_PHY_ADDR 0 341 #define TSEC2_PHY_ADDR 2 342 343 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 344 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 345 346 #define CONFIG_ETHPRIME "eTSEC1" 347 348 #define CONFIG_PHY_GIGE 349 #endif /* CONFIG_TSEC_ENET */ 350 351 /* 352 * Environment 353 */ 354 #if defined(CONFIG_SYS_RAMBOOT) 355 #if defined(CONFIG_RAMBOOT_SPIFLASH) 356 #define CONFIG_ENV_IS_IN_SPI_FLASH 357 #define CONFIG_ENV_SPI_BUS 0 358 #define CONFIG_ENV_SPI_CS 0 359 #define CONFIG_ENV_SPI_MAX_HZ 10000000 360 #define CONFIG_ENV_SPI_MODE 0 361 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 362 #define CONFIG_ENV_SECT_SIZE 0x10000 363 #define CONFIG_ENV_SIZE 0x2000 364 #endif 365 #else 366 #define CONFIG_ENV_IS_IN_FLASH 367 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 368 #define CONFIG_ENV_ADDR 0xfff80000 369 #else 370 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 371 #endif 372 #define CONFIG_ENV_SIZE 0x2000 373 #define CONFIG_ENV_SECT_SIZE 0x20000 374 #endif 375 376 #define CONFIG_LOADS_ECHO 377 #define CONFIG_SYS_LOADS_BAUD_CHANGE 378 379 /* 380 * Command line configuration. 381 */ 382 #include <config_cmd_default.h> 383 384 #define CONFIG_CMD_ERRATA 385 #define CONFIG_CMD_ELF 386 #define CONFIG_CMD_IRQ 387 #define CONFIG_CMD_MII 388 #define CONFIG_CMD_PING 389 #define CONFIG_CMD_SETEXPR 390 #define CONFIG_CMD_REGINFO 391 392 /* 393 * Miscellaneous configurable options 394 */ 395 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 396 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 397 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 398 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 399 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 400 401 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 402 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 403 /* Print Buffer Size */ 404 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 405 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 406 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ 407 408 /* 409 * For booting Linux, the board info and command line data 410 * have to be in the first 64 MB of memory, since this is 411 * the maximum mapped by the Linux kernel during initialization. 412 */ 413 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 414 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 415 416 /* 417 * Environment Configuration 418 */ 419 420 #ifdef CONFIG_TSEC_ENET 421 #define CONFIG_HAS_ETH0 422 #define CONFIG_HAS_ETH1 423 #endif 424 425 #define CONFIG_ROOTPATH "/opt/nfsroot" 426 #define CONFIG_BOOTFILE "uImage" 427 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 428 429 /* default location for tftp and bootm */ 430 #define CONFIG_LOADADDR 1000000 431 432 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 433 434 #define CONFIG_BAUDRATE 115200 435 436 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 437 438 #define CONFIG_EXTRA_ENV_SETTINGS \ 439 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 440 "netdev=eth0\0" \ 441 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 442 "loadaddr=1000000\0" \ 443 "consoledev=ttyS0\0" \ 444 "ramdiskaddr=2000000\0" \ 445 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 446 "fdtaddr=c00000\0" \ 447 "fdtfile=name/of/device-tree.dtb\0" \ 448 "othbootargs=ramdisk_size=600000\0" \ 449 450 #define CONFIG_RAMBOOTCOMMAND \ 451 "setenv bootargs root=/dev/ram rw " \ 452 "console=$consoledev,$baudrate $othbootargs; " \ 453 "tftp $ramdiskaddr $ramdiskfile;" \ 454 "tftp $loadaddr $bootfile;" \ 455 "tftp $fdtaddr $fdtfile;" \ 456 "bootm $loadaddr $ramdiskaddr $fdtaddr" 457 458 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 459 460 #endif /* __CONFIG_H */ 461