1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * B4860 QDS board configuration file 12 */ 13 #define CONFIG_B4860QDS 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 19 #ifndef CONFIG_NAND 20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 22 #else 23 #define CONFIG_SPL 24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 25 #define CONFIG_SPL_ENV_SUPPORT 26 #define CONFIG_SPL_SERIAL_SUPPORT 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_SPL_LIBGENERIC_SUPPORT 30 #define CONFIG_SPL_LIBCOMMON_SUPPORT 31 #define CONFIG_SPL_I2C_SUPPORT 32 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_SYS_TEXT_BASE 0x00201000 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 #define CONFIG_SPL_NAND_SUPPORT 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 46 #define CONFIG_SPL_NAND_BOOT 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #define CONFIG_SYS_NO_FLASH 52 #endif 53 #endif 54 #endif 55 56 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 57 /* Set 1M boot space */ 58 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 59 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 60 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 61 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 62 #define CONFIG_SYS_NO_FLASH 63 #endif 64 65 /* High Level Configuration Options */ 66 #define CONFIG_BOOKE 67 #define CONFIG_E500 /* BOOKE e500 family */ 68 #define CONFIG_E500MC /* BOOKE e500mc family */ 69 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 70 #define CONFIG_MP /* support multiple processors */ 71 72 #ifndef CONFIG_SYS_TEXT_BASE 73 #define CONFIG_SYS_TEXT_BASE 0xeff40000 74 #endif 75 76 #ifndef CONFIG_RESET_VECTOR_ADDRESS 77 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 78 #endif 79 80 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 81 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 82 #define CONFIG_FSL_IFC /* Enable IFC Support */ 83 #define CONFIG_PCI /* Enable PCI/PCIE */ 84 #define CONFIG_PCIE1 /* PCIE controler 1 */ 85 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 86 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 87 88 #ifndef CONFIG_PPC_B4420 89 #define CONFIG_SYS_SRIO 90 #define CONFIG_SRIO1 /* SRIO port 1 */ 91 #define CONFIG_SRIO2 /* SRIO port 2 */ 92 #define CONFIG_SRIO_PCIE_BOOT_MASTER 93 #endif 94 95 #define CONFIG_FSL_LAW /* Use common FSL init code */ 96 97 /* I2C bus multiplexer */ 98 #define I2C_MUX_PCA_ADDR 0x77 99 100 /* VSC Crossbar switches */ 101 #define CONFIG_VSC_CROSSBAR 102 #define I2C_CH_DEFAULT 0x8 103 #define I2C_CH_VSC3316 0xc 104 #define I2C_CH_VSC3308 0xd 105 106 #define VSC3316_TX_ADDRESS 0x70 107 #define VSC3316_RX_ADDRESS 0x71 108 #define VSC3308_TX_ADDRESS 0x02 109 #define VSC3308_RX_ADDRESS 0x03 110 111 /* IDT clock synthesizers */ 112 #define CONFIG_IDT8T49N222A 113 #define I2C_CH_IDT 0x9 114 115 #define IDT_SERDES1_ADDRESS 0x6E 116 #define IDT_SERDES2_ADDRESS 0x6C 117 118 /* Voltage monitor on channel 2*/ 119 #define I2C_MUX_CH_VOL_MONITOR 0xa 120 #define I2C_VOL_MONITOR_ADDR 0x40 121 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 122 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 123 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 124 125 #define CONFIG_ZM7300 126 #define I2C_MUX_CH_DPM 0xa 127 #define I2C_DPM_ADDR 0x28 128 129 #define CONFIG_ENV_OVERWRITE 130 131 #ifdef CONFIG_SYS_NO_FLASH 132 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 133 #define CONFIG_ENV_IS_NOWHERE 134 #endif 135 #else 136 #define CONFIG_FLASH_CFI_DRIVER 137 #define CONFIG_SYS_FLASH_CFI 138 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 139 #endif 140 141 #if defined(CONFIG_SPIFLASH) 142 #define CONFIG_SYS_EXTRA_ENV_RELOC 143 #define CONFIG_ENV_IS_IN_SPI_FLASH 144 #define CONFIG_ENV_SPI_BUS 0 145 #define CONFIG_ENV_SPI_CS 0 146 #define CONFIG_ENV_SPI_MAX_HZ 10000000 147 #define CONFIG_ENV_SPI_MODE 0 148 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 149 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 150 #define CONFIG_ENV_SECT_SIZE 0x10000 151 #elif defined(CONFIG_SDCARD) 152 #define CONFIG_SYS_EXTRA_ENV_RELOC 153 #define CONFIG_ENV_IS_IN_MMC 154 #define CONFIG_SYS_MMC_ENV_DEV 0 155 #define CONFIG_ENV_SIZE 0x2000 156 #define CONFIG_ENV_OFFSET (512 * 1097) 157 #elif defined(CONFIG_NAND) 158 #define CONFIG_SYS_EXTRA_ENV_RELOC 159 #define CONFIG_ENV_IS_IN_NAND 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 162 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 163 #define CONFIG_ENV_IS_IN_REMOTE 164 #define CONFIG_ENV_ADDR 0xffe20000 165 #define CONFIG_ENV_SIZE 0x2000 166 #elif defined(CONFIG_ENV_IS_NOWHERE) 167 #define CONFIG_ENV_SIZE 0x2000 168 #else 169 #define CONFIG_ENV_IS_IN_FLASH 170 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 171 #define CONFIG_ENV_SIZE 0x2000 172 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 173 #endif 174 175 #ifndef __ASSEMBLY__ 176 unsigned long get_board_sys_clk(void); 177 unsigned long get_board_ddr_clk(void); 178 #endif 179 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 180 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 181 182 /* 183 * These can be toggled for performance analysis, otherwise use default. 184 */ 185 #define CONFIG_SYS_CACHE_STASHING 186 #define CONFIG_BTB /* toggle branch predition */ 187 #define CONFIG_DDR_ECC 188 #ifdef CONFIG_DDR_ECC 189 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 190 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 191 #endif 192 193 #define CONFIG_ENABLE_36BIT_PHYS 194 195 #ifdef CONFIG_PHYS_64BIT 196 #define CONFIG_ADDR_MAP 197 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 198 #endif 199 200 #if 0 201 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 202 #endif 203 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 204 #define CONFIG_SYS_MEMTEST_END 0x00400000 205 #define CONFIG_SYS_ALT_MEMTEST 206 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 207 208 /* 209 * Config the L3 Cache as L3 SRAM 210 */ 211 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 212 #define CONFIG_SYS_L3_SIZE 256 << 10 213 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 214 #ifdef CONFIG_NAND 215 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 216 #endif 217 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 218 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 219 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 220 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 221 222 #ifdef CONFIG_PHYS_64BIT 223 #define CONFIG_SYS_DCSRBAR 0xf0000000 224 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 225 #endif 226 227 /* EEPROM */ 228 #define CONFIG_SYS_I2C_EEPROM_NXID 229 #define CONFIG_SYS_EEPROM_BUS_NUM 0 230 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 231 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 234 235 /* 236 * DDR Setup 237 */ 238 #define CONFIG_VERY_BIG_RAM 239 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 240 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 241 242 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 243 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 244 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 245 246 #define CONFIG_DDR_SPD 247 #define CONFIG_SYS_DDR_RAW_TIMING 248 #define CONFIG_SYS_FSL_DDR3 249 #ifndef CONFIG_SPL_BUILD 250 #define CONFIG_FSL_DDR_INTERACTIVE 251 #endif 252 253 #define CONFIG_SYS_SPD_BUS_NUM 0 254 #define SPD_EEPROM_ADDRESS1 0x51 255 #define SPD_EEPROM_ADDRESS2 0x53 256 257 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 258 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 259 260 /* 261 * IFC Definitions 262 */ 263 #define CONFIG_SYS_FLASH_BASE 0xe0000000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 266 #else 267 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 268 #endif 269 270 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 271 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 272 + 0x8000000) | \ 273 CSPR_PORT_SIZE_16 | \ 274 CSPR_MSEL_NOR | \ 275 CSPR_V) 276 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 277 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 278 CSPR_PORT_SIZE_16 | \ 279 CSPR_MSEL_NOR | \ 280 CSPR_V) 281 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 282 /* NOR Flash Timing Params */ 283 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 284 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 285 FTIM0_NOR_TEADC(0x04) | \ 286 FTIM0_NOR_TEAHC(0x20)) 287 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 288 FTIM1_NOR_TRAD_NOR(0x1A) |\ 289 FTIM1_NOR_TSEQRAD_NOR(0x13)) 290 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 291 FTIM2_NOR_TCH(0x0E) | \ 292 FTIM2_NOR_TWPH(0x0E) | \ 293 FTIM2_NOR_TWP(0x1c)) 294 #define CONFIG_SYS_NOR_FTIM3 0x0 295 296 #define CONFIG_SYS_FLASH_QUIET_TEST 297 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 298 299 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 300 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 301 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 302 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 303 304 #define CONFIG_SYS_FLASH_EMPTY_INFO 305 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 306 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 307 308 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 309 #define CONFIG_FSL_QIXIS_V2 310 #define QIXIS_BASE 0xffdf0000 311 #ifdef CONFIG_PHYS_64BIT 312 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 313 #else 314 #define QIXIS_BASE_PHYS QIXIS_BASE 315 #endif 316 #define QIXIS_LBMAP_SWITCH 0x01 317 #define QIXIS_LBMAP_MASK 0x0f 318 #define QIXIS_LBMAP_SHIFT 0 319 #define QIXIS_LBMAP_DFLTBANK 0x00 320 #define QIXIS_LBMAP_ALTBANK 0x02 321 #define QIXIS_RST_CTL_RESET 0x31 322 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 323 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 324 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 325 326 #define CONFIG_SYS_CSPR3_EXT (0xf) 327 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 328 | CSPR_PORT_SIZE_8 \ 329 | CSPR_MSEL_GPCM \ 330 | CSPR_V) 331 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 332 #define CONFIG_SYS_CSOR3 0x0 333 /* QIXIS Timing parameters for IFC CS3 */ 334 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 335 FTIM0_GPCM_TEADC(0x0e) | \ 336 FTIM0_GPCM_TEAHC(0x0e)) 337 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 338 FTIM1_GPCM_TRAD(0x1f)) 339 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 340 FTIM2_GPCM_TCH(0x0) | \ 341 FTIM2_GPCM_TWP(0x1f)) 342 #define CONFIG_SYS_CS3_FTIM3 0x0 343 344 /* NAND Flash on IFC */ 345 #define CONFIG_NAND_FSL_IFC 346 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 347 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 348 #define CONFIG_SYS_NAND_BASE 0xff800000 349 #ifdef CONFIG_PHYS_64BIT 350 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 351 #else 352 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 353 #endif 354 355 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 356 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 357 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 358 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 359 | CSPR_V) 360 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 361 362 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 363 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 364 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 365 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 366 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 367 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 368 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 369 370 #define CONFIG_SYS_NAND_ONFI_DETECTION 371 372 /* ONFI NAND Flash mode0 Timing Params */ 373 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 374 FTIM0_NAND_TWP(0x18) | \ 375 FTIM0_NAND_TWCHT(0x07) | \ 376 FTIM0_NAND_TWH(0x0a)) 377 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 378 FTIM1_NAND_TWBE(0x39) | \ 379 FTIM1_NAND_TRR(0x0e) | \ 380 FTIM1_NAND_TRP(0x18)) 381 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 382 FTIM2_NAND_TREH(0x0a) | \ 383 FTIM2_NAND_TWHRE(0x1e)) 384 #define CONFIG_SYS_NAND_FTIM3 0x0 385 386 #define CONFIG_SYS_NAND_DDR_LAW 11 387 388 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 389 #define CONFIG_SYS_MAX_NAND_DEVICE 1 390 #define CONFIG_MTD_NAND_VERIFY_WRITE 391 #define CONFIG_CMD_NAND 392 393 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 394 395 #if defined(CONFIG_NAND) 396 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 397 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 398 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 399 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 400 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 401 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 402 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 403 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 404 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 405 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 406 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 407 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 408 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 409 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 410 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 411 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 412 #else 413 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 414 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 415 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 416 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 417 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 418 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 419 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 420 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 421 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 422 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 423 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 424 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 425 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 426 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 427 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 428 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 429 #endif 430 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 431 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 432 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 433 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 434 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 435 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 436 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 437 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 438 439 #ifdef CONFIG_SPL_BUILD 440 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 441 #else 442 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 443 #endif 444 445 #if defined(CONFIG_RAMBOOT_PBL) 446 #define CONFIG_SYS_RAMBOOT 447 #endif 448 449 #define CONFIG_BOARD_EARLY_INIT_R 450 #define CONFIG_MISC_INIT_R 451 452 #define CONFIG_HWCONFIG 453 454 /* define to use L1 as initial stack */ 455 #define CONFIG_L1_INIT_RAM 456 #define CONFIG_SYS_INIT_RAM_LOCK 457 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 461 /* The assembler doesn't like typecast */ 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 463 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 464 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 465 #else 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 469 #endif 470 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 471 472 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 473 GENERATED_GBL_DATA_SIZE) 474 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 475 476 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 477 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 478 479 /* Serial Port - controlled on board with jumper J8 480 * open - index 2 481 * shorted - index 1 482 */ 483 #define CONFIG_CONS_INDEX 1 484 #define CONFIG_SYS_NS16550 485 #define CONFIG_SYS_NS16550_SERIAL 486 #define CONFIG_SYS_NS16550_REG_SIZE 1 487 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 488 489 #define CONFIG_SYS_BAUDRATE_TABLE \ 490 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 491 492 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 493 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 494 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 495 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 496 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 497 #ifndef CONFIG_SPL_BUILD 498 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 499 #endif 500 501 502 /* Use the HUSH parser */ 503 #define CONFIG_SYS_HUSH_PARSER 504 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 505 506 /* pass open firmware flat tree */ 507 #define CONFIG_OF_LIBFDT 508 #define CONFIG_OF_BOARD_SETUP 509 #define CONFIG_OF_STDOUT_VIA_ALIAS 510 511 /* new uImage format support */ 512 #define CONFIG_FIT 513 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 514 515 /* I2C */ 516 #define CONFIG_SYS_I2C 517 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 518 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 519 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 520 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 521 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 522 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 523 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 524 525 /* 526 * RTC configuration 527 */ 528 #define RTC 529 #define CONFIG_RTC_DS3231 1 530 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 531 532 /* 533 * RapidIO 534 */ 535 #ifdef CONFIG_SYS_SRIO 536 #ifdef CONFIG_SRIO1 537 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 540 #else 541 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 542 #endif 543 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 544 #endif 545 546 #ifdef CONFIG_SRIO2 547 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 548 #ifdef CONFIG_PHYS_64BIT 549 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 550 #else 551 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 552 #endif 553 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 554 #endif 555 #endif 556 557 /* 558 * for slave u-boot IMAGE instored in master memory space, 559 * PHYS must be aligned based on the SIZE 560 */ 561 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 562 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 563 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 564 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 565 /* 566 * for slave UCODE and ENV instored in master memory space, 567 * PHYS must be aligned based on the SIZE 568 */ 569 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 570 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 571 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 572 573 /* slave core release by master*/ 574 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 575 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 576 577 /* 578 * SRIO_PCIE_BOOT - SLAVE 579 */ 580 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 581 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 582 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 583 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 584 #endif 585 586 /* 587 * eSPI - Enhanced SPI 588 */ 589 #define CONFIG_FSL_ESPI 590 #define CONFIG_SPI_FLASH 591 #define CONFIG_SPI_FLASH_SST 592 #define CONFIG_CMD_SF 593 #define CONFIG_SF_DEFAULT_SPEED 10000000 594 #define CONFIG_SF_DEFAULT_MODE 0 595 596 /* 597 * MAPLE 598 */ 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 601 #else 602 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 603 #endif 604 605 /* 606 * General PCI 607 * Memory space is mapped 1-1, but I/O space must start from 0. 608 */ 609 610 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 611 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 612 #ifdef CONFIG_PHYS_64BIT 613 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 614 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 615 #else 616 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 617 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 618 #endif 619 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 620 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 621 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 622 #ifdef CONFIG_PHYS_64BIT 623 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 624 #else 625 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 626 #endif 627 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 628 629 /* Qman/Bman */ 630 #ifndef CONFIG_NOBQFMAN 631 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 632 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 633 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 634 #ifdef CONFIG_PHYS_64BIT 635 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 636 #else 637 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 638 #endif 639 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 640 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 641 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 642 #ifdef CONFIG_PHYS_64BIT 643 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 644 #else 645 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 646 #endif 647 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 648 649 #define CONFIG_SYS_DPAA_FMAN 650 651 #define CONFIG_SYS_DPAA_RMAN 652 653 /* Default address of microcode for the Linux Fman driver */ 654 #if defined(CONFIG_SPIFLASH) 655 /* 656 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 657 * env, so we got 0x110000. 658 */ 659 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 660 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 661 #elif defined(CONFIG_SDCARD) 662 /* 663 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 664 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 665 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 666 */ 667 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 668 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 669 #elif defined(CONFIG_NAND) 670 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 671 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 672 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 673 /* 674 * Slave has no ucode locally, it can fetch this from remote. When implementing 675 * in two corenet boards, slave's ucode could be stored in master's memory 676 * space, the address can be mapped from slave TLB->slave LAW-> 677 * slave SRIO or PCIE outbound window->master inbound window-> 678 * master LAW->the ucode address in master's memory space. 679 */ 680 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 681 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 682 #else 683 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 684 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 685 #endif 686 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 687 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 688 #endif /* CONFIG_NOBQFMAN */ 689 690 #ifdef CONFIG_SYS_DPAA_FMAN 691 #define CONFIG_FMAN_ENET 692 #define CONFIG_PHYLIB_10G 693 #define CONFIG_PHY_VITESSE 694 #define CONFIG_PHY_TERANETICS 695 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 696 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 697 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 698 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 699 #endif 700 701 #ifdef CONFIG_PCI 702 #define CONFIG_PCI_INDIRECT_BRIDGE 703 #define CONFIG_NET_MULTI 704 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 705 #define CONFIG_E1000 706 707 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 708 #define CONFIG_DOS_PARTITION 709 #endif /* CONFIG_PCI */ 710 711 #ifdef CONFIG_FMAN_ENET 712 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 713 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 714 715 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 716 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 717 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 718 719 720 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 721 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 722 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 723 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 724 725 #define CONFIG_MII /* MII PHY management */ 726 #define CONFIG_ETHPRIME "FM1@DTSEC1" 727 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 728 #endif 729 730 /* 731 * Environment 732 */ 733 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 734 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 735 736 /* 737 * Command line configuration. 738 */ 739 #include <config_cmd_default.h> 740 741 #define CONFIG_CMD_DATE 742 #define CONFIG_CMD_DHCP 743 #define CONFIG_CMD_EEPROM 744 #define CONFIG_CMD_ELF 745 #define CONFIG_CMD_ERRATA 746 #define CONFIG_CMD_GREPENV 747 #define CONFIG_CMD_IRQ 748 #define CONFIG_CMD_I2C 749 #define CONFIG_CMD_MII 750 #define CONFIG_CMD_PING 751 #define CONFIG_CMD_REGINFO 752 #define CONFIG_CMD_SETEXPR 753 754 #ifdef CONFIG_PCI 755 #define CONFIG_CMD_PCI 756 #define CONFIG_CMD_NET 757 #endif 758 759 /* 760 * USB 761 */ 762 #define CONFIG_HAS_FSL_DR_USB 763 764 #ifdef CONFIG_HAS_FSL_DR_USB 765 #define CONFIG_USB_EHCI 766 767 #ifdef CONFIG_USB_EHCI 768 #define CONFIG_CMD_USB 769 #define CONFIG_USB_STORAGE 770 #define CONFIG_USB_EHCI_FSL 771 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 772 #define CONFIG_CMD_EXT2 773 #endif 774 #endif 775 776 /* 777 * Miscellaneous configurable options 778 */ 779 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 780 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 781 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 782 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 783 #ifdef CONFIG_CMD_KGDB 784 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 785 #else 786 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 787 #endif 788 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 789 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 790 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 791 792 /* 793 * For booting Linux, the board info and command line data 794 * have to be in the first 64 MB of memory, since this is 795 * the maximum mapped by the Linux kernel during initialization. 796 */ 797 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 798 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 799 800 #ifdef CONFIG_CMD_KGDB 801 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 802 #endif 803 804 /* 805 * Environment Configuration 806 */ 807 #define CONFIG_ROOTPATH "/opt/nfsroot" 808 #define CONFIG_BOOTFILE "uImage" 809 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 810 811 /* default location for tftp and bootm */ 812 #define CONFIG_LOADADDR 1000000 813 814 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 815 816 #define CONFIG_BAUDRATE 115200 817 818 #define __USB_PHY_TYPE ulpi 819 820 #define CONFIG_EXTRA_ENV_SETTINGS \ 821 "hwconfig=fsl_ddr:ctlr_intlv=null," \ 822 "bank_intlv=cs0_cs1;" \ 823 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 824 "netdev=eth0\0" \ 825 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 826 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 827 "tftpflash=tftpboot $loadaddr $uboot && " \ 828 "protect off $ubootaddr +$filesize && " \ 829 "erase $ubootaddr +$filesize && " \ 830 "cp.b $loadaddr $ubootaddr $filesize && " \ 831 "protect on $ubootaddr +$filesize && " \ 832 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 833 "consoledev=ttyS0\0" \ 834 "ramdiskaddr=2000000\0" \ 835 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 836 "fdtaddr=c00000\0" \ 837 "fdtfile=b4860qds/b4860qds.dtb\0" \ 838 "bdev=sda3\0" \ 839 "c=ffe\0" 840 841 /* For emulation this causes u-boot to jump to the start of the proof point 842 app code automatically */ 843 #define CONFIG_PROOF_POINTS \ 844 "setenv bootargs root=/dev/$bdev rw " \ 845 "console=$consoledev,$baudrate $othbootargs;" \ 846 "cpu 1 release 0x29000000 - - -;" \ 847 "cpu 2 release 0x29000000 - - -;" \ 848 "cpu 3 release 0x29000000 - - -;" \ 849 "cpu 4 release 0x29000000 - - -;" \ 850 "cpu 5 release 0x29000000 - - -;" \ 851 "cpu 6 release 0x29000000 - - -;" \ 852 "cpu 7 release 0x29000000 - - -;" \ 853 "go 0x29000000" 854 855 #define CONFIG_HVBOOT \ 856 "setenv bootargs config-addr=0x60000000; " \ 857 "bootm 0x01000000 - 0x00f00000" 858 859 #define CONFIG_ALU \ 860 "setenv bootargs root=/dev/$bdev rw " \ 861 "console=$consoledev,$baudrate $othbootargs;" \ 862 "cpu 1 release 0x01000000 - - -;" \ 863 "cpu 2 release 0x01000000 - - -;" \ 864 "cpu 3 release 0x01000000 - - -;" \ 865 "cpu 4 release 0x01000000 - - -;" \ 866 "cpu 5 release 0x01000000 - - -;" \ 867 "cpu 6 release 0x01000000 - - -;" \ 868 "cpu 7 release 0x01000000 - - -;" \ 869 "go 0x01000000" 870 871 #define CONFIG_LINUX \ 872 "setenv bootargs root=/dev/ram rw " \ 873 "console=$consoledev,$baudrate $othbootargs;" \ 874 "setenv ramdiskaddr 0x02000000;" \ 875 "setenv fdtaddr 0x00c00000;" \ 876 "setenv loadaddr 0x1000000;" \ 877 "bootm $loadaddr $ramdiskaddr $fdtaddr" 878 879 #define CONFIG_HDBOOT \ 880 "setenv bootargs root=/dev/$bdev rw " \ 881 "console=$consoledev,$baudrate $othbootargs;" \ 882 "tftp $loadaddr $bootfile;" \ 883 "tftp $fdtaddr $fdtfile;" \ 884 "bootm $loadaddr - $fdtaddr" 885 886 #define CONFIG_NFSBOOTCOMMAND \ 887 "setenv bootargs root=/dev/nfs rw " \ 888 "nfsroot=$serverip:$rootpath " \ 889 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 890 "console=$consoledev,$baudrate $othbootargs;" \ 891 "tftp $loadaddr $bootfile;" \ 892 "tftp $fdtaddr $fdtfile;" \ 893 "bootm $loadaddr - $fdtaddr" 894 895 #define CONFIG_RAMBOOTCOMMAND \ 896 "setenv bootargs root=/dev/ram rw " \ 897 "console=$consoledev,$baudrate $othbootargs;" \ 898 "tftp $ramdiskaddr $ramdiskfile;" \ 899 "tftp $loadaddr $bootfile;" \ 900 "tftp $fdtaddr $fdtfile;" \ 901 "bootm $loadaddr $ramdiskaddr $fdtaddr" 902 903 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 904 905 #include <asm/fsl_secure_boot.h> 906 907 #endif /* __CONFIG_H */ 908