xref: /openbmc/u-boot/include/altera.h (revision 5c676780e116dc79c1819d6c49a2aa53e1053e04)
183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2c609719bSwdenk /*
3c609719bSwdenk  * (C) Copyright 2002
4c609719bSwdenk  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5c609719bSwdenk  */
6c609719bSwdenk 
7c609719bSwdenk #include <fpga.h>
8c609719bSwdenk 
9c609719bSwdenk #ifndef _ALTERA_H_
10c609719bSwdenk #define _ALTERA_H_
11c609719bSwdenk 
12ff9c4c53SStefan Roese /*
13ff9c4c53SStefan Roese  * For the StratixV FPGA programming via SPI, the following
14ff9c4c53SStefan Roese  * information is coded in the 32bit cookie:
15ff9c4c53SStefan Roese  * Bit 31 ... Bit 0
16ff9c4c53SStefan Roese  * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
17ff9c4c53SStefan Roese  */
18ff9c4c53SStefan Roese #define FPGA_COOKIE(bus, dev, config, done)			\
19ff9c4c53SStefan Roese 	(((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
20ff9c4c53SStefan Roese #define COOKIE2SPI_BUS(c)	(((c) >> 24) & 0xff)
21ff9c4c53SStefan Roese #define COOKIE2SPI_DEV(c)	(((c) >> 16) & 0xff)
22ff9c4c53SStefan Roese #define COOKIE2CONFIG(c)	(((c) >> 8) & 0xff)
23ff9c4c53SStefan Roese #define COOKIE2DONE(c)		((c) & 0xff)
24ff9c4c53SStefan Roese 
25d44ef7ffSMarek Vasut enum altera_iface {
26d44ef7ffSMarek Vasut 	/* insert all new types after this */
27d44ef7ffSMarek Vasut 	min_altera_iface_type,
28d44ef7ffSMarek Vasut 	/* serial data and external clock */
29d44ef7ffSMarek Vasut 	passive_serial,
30d44ef7ffSMarek Vasut 	/* parallel data */
31d44ef7ffSMarek Vasut 	passive_parallel_synchronous,
32d44ef7ffSMarek Vasut 	/* parallel data */
33d44ef7ffSMarek Vasut 	passive_parallel_asynchronous,
34d44ef7ffSMarek Vasut 	/* serial data w/ internal clock (not used) */
35d44ef7ffSMarek Vasut 	passive_serial_asynchronous,
36d44ef7ffSMarek Vasut 	/* jtag/tap serial (not used ) */
37d44ef7ffSMarek Vasut 	altera_jtag_mode,
38d44ef7ffSMarek Vasut 	/* fast passive parallel (FPP) */
39d44ef7ffSMarek Vasut 	fast_passive_parallel,
40d44ef7ffSMarek Vasut 	/* fast passive parallel with security (FPPS) */
41d44ef7ffSMarek Vasut 	fast_passive_parallel_security,
42*877ec6ebSAng, Chee Hong 	/* secure device manager (SDM) mailbox */
43*877ec6ebSAng, Chee Hong 	secure_device_manager_mailbox,
44d44ef7ffSMarek Vasut 	/* insert all new types before this */
45d44ef7ffSMarek Vasut 	max_altera_iface_type,
46d44ef7ffSMarek Vasut };
47c609719bSwdenk 
48d44ef7ffSMarek Vasut enum altera_family {
49d44ef7ffSMarek Vasut 	/* insert all new types after this */
50d44ef7ffSMarek Vasut 	min_altera_type,
51d44ef7ffSMarek Vasut 	/* ACEX1K Family */
52d44ef7ffSMarek Vasut 	Altera_ACEX1K,
53d44ef7ffSMarek Vasut 	/* CYCLONII Family */
54d44ef7ffSMarek Vasut 	Altera_CYC2,
55d44ef7ffSMarek Vasut 	/* StratixII Family */
56d44ef7ffSMarek Vasut 	Altera_StratixII,
57ff9c4c53SStefan Roese 	/* StratixV Family */
58ff9c4c53SStefan Roese 	Altera_StratixV,
59*877ec6ebSAng, Chee Hong 	/* Stratix10 Family */
60*877ec6ebSAng, Chee Hong 	Intel_FPGA_Stratix10,
61230fe9b2SPavel Machek 	/* SoCFPGA Family */
62230fe9b2SPavel Machek 	Altera_SoCFPGA,
63d44ef7ffSMarek Vasut 
64c609719bSwdenk 	/* Add new models here */
65c609719bSwdenk 
66d44ef7ffSMarek Vasut 	/* insert all new types before this */
67d44ef7ffSMarek Vasut 	max_altera_type,
68d44ef7ffSMarek Vasut };
69d44ef7ffSMarek Vasut 
70d44ef7ffSMarek Vasut typedef struct {
71d44ef7ffSMarek Vasut 	/* part type */
72d44ef7ffSMarek Vasut 	enum altera_family	family;
73d44ef7ffSMarek Vasut 	/* interface type */
74d44ef7ffSMarek Vasut 	enum altera_iface	iface;
75d44ef7ffSMarek Vasut 	/* bytes of data part can accept */
76d44ef7ffSMarek Vasut 	size_t			size;
77d44ef7ffSMarek Vasut 	/* interface function table */
78d44ef7ffSMarek Vasut 	void			*iface_fns;
79d44ef7ffSMarek Vasut 	/* base interface address */
80d44ef7ffSMarek Vasut 	void			*base;
81d44ef7ffSMarek Vasut 	/* implementation specific cookie */
82d44ef7ffSMarek Vasut 	int			cookie;
83d44ef7ffSMarek Vasut } Altera_desc;
84c609719bSwdenk 
855da627a4Swdenk /* Generic Altera Functions
865da627a4Swdenk  *********************************************************************/
87e6a857daSWolfgang Denk extern int altera_load(Altera_desc *desc, const void *image, size_t size);
88e6a857daSWolfgang Denk extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
89c609719bSwdenk extern int altera_info(Altera_desc *desc);
905da627a4Swdenk 
915da627a4Swdenk /* Board specific implementation specific function types
925da627a4Swdenk  *********************************************************************/
935da627a4Swdenk typedef int (*Altera_pre_fn)( int cookie );
945da627a4Swdenk typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
955da627a4Swdenk typedef int (*Altera_status_fn)( int cookie );
965da627a4Swdenk typedef int (*Altera_done_fn)( int cookie );
975da627a4Swdenk typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
985da627a4Swdenk typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
99e6a857daSWolfgang Denk typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
1005da627a4Swdenk typedef int (*Altera_abort_fn)( int cookie );
1015da627a4Swdenk typedef int (*Altera_post_fn)( int cookie );
102c609719bSwdenk 
1033c735e74Seran liberty typedef struct {
1043c735e74Seran liberty 	Altera_pre_fn pre;
1053c735e74Seran liberty 	Altera_config_fn config;
1063c735e74Seran liberty 	Altera_status_fn status;
1073c735e74Seran liberty 	Altera_done_fn done;
1083c735e74Seran liberty 	Altera_clk_fn clk;
1093c735e74Seran liberty 	Altera_data_fn data;
110ff9c4c53SStefan Roese 	Altera_write_fn write;
1113c735e74Seran liberty 	Altera_abort_fn abort;
1123c735e74Seran liberty 	Altera_post_fn post;
1133c735e74Seran liberty } altera_board_specific_func;
1143c735e74Seran liberty 
115230fe9b2SPavel Machek #ifdef CONFIG_FPGA_SOCFPGA
116230fe9b2SPavel Machek int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
117230fe9b2SPavel Machek #endif
118230fe9b2SPavel Machek 
119ff9c4c53SStefan Roese #ifdef CONFIG_FPGA_STRATIX_V
120ff9c4c53SStefan Roese int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
121ff9c4c53SStefan Roese #endif
122ff9c4c53SStefan Roese 
123c41e660bSAng, Chee Hong #ifdef CONFIG_FPGA_STRATIX10
124c41e660bSAng, Chee Hong int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
125c41e660bSAng, Chee Hong #endif
126c41e660bSAng, Chee Hong 
127c609719bSwdenk #endif /* _ALTERA_H_ */
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