1abbab703STroy Kisky /* 2abbab703STroy Kisky * watchdog.c - driver for i.mx on-chip watchdog 3abbab703STroy Kisky * 4abbab703STroy Kisky * Licensed under the GPL-2 or later. 5abbab703STroy Kisky */ 6abbab703STroy Kisky 7abbab703STroy Kisky #include <common.h> 8abbab703STroy Kisky #include <asm/io.h> 9abbab703STroy Kisky #include <watchdog.h> 10abbab703STroy Kisky #include <asm/arch/imx-regs.h> 11abbab703STroy Kisky 12abbab703STroy Kisky struct watchdog_regs { 13abbab703STroy Kisky u16 wcr; /* Control */ 14abbab703STroy Kisky u16 wsr; /* Service */ 15abbab703STroy Kisky u16 wrsr; /* Reset Status */ 16abbab703STroy Kisky }; 17abbab703STroy Kisky 18abbab703STroy Kisky #define WCR_WDZST 0x01 19abbab703STroy Kisky #define WCR_WDBG 0x02 20abbab703STroy Kisky #define WCR_WDE 0x04 /* WDOG enable */ 21abbab703STroy Kisky #define WCR_WDT 0x08 22*723ec69aSAnatolij Gustschin #define WCR_SRS 0x10 23abbab703STroy Kisky #define WCR_WDW 0x80 24abbab703STroy Kisky #define SET_WCR_WT(x) (x << 8) 25abbab703STroy Kisky 26abbab703STroy Kisky #ifdef CONFIG_IMX_WATCHDOG 27abbab703STroy Kisky void hw_watchdog_reset(void) 28abbab703STroy Kisky { 29abbab703STroy Kisky struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 30abbab703STroy Kisky 31abbab703STroy Kisky writew(0x5555, &wdog->wsr); 32abbab703STroy Kisky writew(0xaaaa, &wdog->wsr); 33abbab703STroy Kisky } 34abbab703STroy Kisky 35abbab703STroy Kisky void hw_watchdog_init(void) 36abbab703STroy Kisky { 37abbab703STroy Kisky struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 38abbab703STroy Kisky u16 timeout; 39abbab703STroy Kisky 40abbab703STroy Kisky /* 41abbab703STroy Kisky * The timer watchdog can be set between 42abbab703STroy Kisky * 0.5 and 128 Seconds. If not defined 43abbab703STroy Kisky * in configuration file, sets 128 Seconds 44abbab703STroy Kisky */ 45abbab703STroy Kisky #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS 46abbab703STroy Kisky #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 47abbab703STroy Kisky #endif 48abbab703STroy Kisky timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; 49*723ec69aSAnatolij Gustschin writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | 50abbab703STroy Kisky WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); 51abbab703STroy Kisky hw_watchdog_reset(); 52abbab703STroy Kisky } 53abbab703STroy Kisky #endif 54abbab703STroy Kisky 55abbab703STroy Kisky void reset_cpu(ulong addr) 56abbab703STroy Kisky { 57abbab703STroy Kisky struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 58abbab703STroy Kisky 59abbab703STroy Kisky writew(WCR_WDE, &wdog->wcr); 60abbab703STroy Kisky writew(0x5555, &wdog->wsr); 61abbab703STroy Kisky writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ 62abbab703STroy Kisky while (1) { 63abbab703STroy Kisky /* 64abbab703STroy Kisky * spin for .5 seconds before reset 65abbab703STroy Kisky */ 66abbab703STroy Kisky } 67abbab703STroy Kisky } 68