1 /* 2 * Copyright (c) 2011-2013, NVIDIA Corporation. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <panel.h> 12 #include <syscon.h> 13 #include <video_bridge.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch-tegra/dc.h> 17 #include "displayport.h" 18 #include "sor.h" 19 20 #define DEBUG_SOR 0 21 22 #define APBDEV_PMC_DPD_SAMPLE 0x20 23 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE 0 24 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE 1 25 #define APBDEV_PMC_SEL_DPD_TIM 0x1c8 26 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT 0x7f 27 #define APBDEV_PMC_IO_DPD2_REQ 0x1c0 28 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT 25 29 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25) 30 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25) 31 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT 30 32 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30) 33 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30) 34 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30) 35 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30) 36 #define APBDEV_PMC_IO_DPD2_STATUS 0x1c4 37 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT 25 38 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25) 39 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25) 40 41 struct tegra_dc_sor_data { 42 void *base; 43 void *pmc_base; 44 u8 portnum; /* 0 or 1 */ 45 int power_is_up; 46 struct udevice *panel; 47 }; 48 49 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) 50 { 51 return readl((u32 *)sor->base + reg); 52 } 53 54 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg, 55 u32 val) 56 { 57 writel(val, (u32 *)sor->base + reg); 58 } 59 60 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, 61 u32 reg, u32 mask, u32 val) 62 { 63 u32 reg_val = tegra_sor_readl(sor, reg); 64 reg_val &= ~mask; 65 reg_val |= val; 66 tegra_sor_writel(sor, reg, reg_val); 67 } 68 69 void tegra_dp_disable_tx_pu(struct udevice *dev) 70 { 71 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 72 73 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 74 DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE); 75 } 76 77 void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg, 78 u32 vs_reg, u32 pc_reg, u8 pc_supported) 79 { 80 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 81 82 tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg); 83 tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg); 84 if (pc_supported) { 85 tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask, 86 pc_reg); 87 } 88 } 89 90 static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg, 91 u32 mask, u32 exp_val, 92 int poll_interval_us, int timeout_ms) 93 { 94 u32 reg_val = 0; 95 ulong start; 96 97 start = get_timer(0); 98 do { 99 reg_val = tegra_sor_readl(sor, reg); 100 if (((reg_val & mask) == exp_val)) 101 return 0; 102 udelay(poll_interval_us); 103 } while (get_timer(start) < timeout_ms); 104 105 debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", 106 reg, reg_val, mask, exp_val); 107 108 return -ETIMEDOUT; 109 } 110 111 int tegra_dc_sor_set_power_state(struct udevice *dev, int pu_pd) 112 { 113 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 114 u32 reg_val; 115 u32 orig_val; 116 117 orig_val = tegra_sor_readl(sor, PWR); 118 119 reg_val = pu_pd ? PWR_NORMAL_STATE_PU : 120 PWR_NORMAL_STATE_PD; /* normal state only */ 121 122 if (reg_val == orig_val) 123 return 0; /* No update needed */ 124 125 reg_val |= PWR_SETTING_NEW_TRIGGER; 126 tegra_sor_writel(sor, PWR, reg_val); 127 128 /* Poll to confirm it is done */ 129 if (tegra_dc_sor_poll_register(sor, PWR, 130 PWR_SETTING_NEW_DEFAULT_MASK, 131 PWR_SETTING_NEW_DONE, 132 100, TEGRA_SOR_TIMEOUT_MS)) { 133 debug("dc timeout waiting for SOR_PWR = NEW_DONE\n"); 134 return -EFAULT; 135 } 136 137 return 0; 138 } 139 140 void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena, 141 u8 training_pattern, 142 const struct tegra_dp_link_config *link_cfg) 143 { 144 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 145 u32 reg_val; 146 147 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); 148 149 if (ena) 150 reg_val |= DP_LINKCTL_ENABLE_YES; 151 else 152 reg_val &= DP_LINKCTL_ENABLE_NO; 153 154 reg_val &= ~DP_LINKCTL_TUSIZE_MASK; 155 reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT); 156 157 if (link_cfg->enhanced_framing) 158 reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE; 159 160 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); 161 162 switch (training_pattern) { 163 case training_pattern_1: 164 tegra_sor_writel(sor, DP_TPG, 0x41414141); 165 break; 166 case training_pattern_2: 167 case training_pattern_3: 168 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ? 169 0x43434343 : 0x42424242; 170 tegra_sor_writel(sor, DP_TPG, reg_val); 171 break; 172 default: 173 tegra_sor_writel(sor, DP_TPG, 0x50505050); 174 break; 175 } 176 } 177 178 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor, 179 int pu, int is_lvds) 180 { 181 u32 reg_val; 182 183 /* SOR lane sequencer */ 184 if (pu) { 185 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | 186 LANE_SEQ_CTL_SEQUENCE_DOWN | 187 LANE_SEQ_CTL_NEW_POWER_STATE_PU; 188 } else { 189 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER | 190 LANE_SEQ_CTL_SEQUENCE_UP | 191 LANE_SEQ_CTL_NEW_POWER_STATE_PD; 192 } 193 194 if (is_lvds) 195 reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT; 196 else 197 reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT; 198 199 tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val); 200 201 if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL, 202 LANE_SEQ_CTL_SETTING_MASK, 203 LANE_SEQ_CTL_SETTING_NEW_DONE, 204 100, TEGRA_SOR_TIMEOUT_MS)) { 205 debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n"); 206 return -1; 207 } 208 209 return 0; 210 } 211 212 static int tegra_dc_sor_power_dplanes(struct udevice *dev, 213 u32 lane_count, int pu) 214 { 215 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 216 u32 reg_val; 217 218 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); 219 220 if (pu) { 221 switch (lane_count) { 222 case 4: 223 reg_val |= (DP_PADCTL_PD_TXD_3_NO | 224 DP_PADCTL_PD_TXD_2_NO); 225 /* fall through */ 226 case 2: 227 reg_val |= DP_PADCTL_PD_TXD_1_NO; 228 case 1: 229 reg_val |= DP_PADCTL_PD_TXD_0_NO; 230 break; 231 default: 232 debug("dp: invalid lane number %d\n", lane_count); 233 return -1; 234 } 235 236 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); 237 tegra_dc_sor_set_lane_count(dev, lane_count); 238 } 239 240 return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0); 241 } 242 243 void tegra_dc_sor_set_panel_power(struct udevice *dev, int power_up) 244 { 245 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 246 u32 reg_val; 247 248 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); 249 250 if (power_up) 251 reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP; 252 else 253 reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP; 254 255 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); 256 } 257 258 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div, 259 u32 pwm_dutycycle) 260 { 261 tegra_sor_writel(sor, PWM_DIV, pwm_div); 262 tegra_sor_writel(sor, PWM_CTL, 263 (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) | 264 PWM_CTL_SETTING_NEW_TRIGGER); 265 266 if (tegra_dc_sor_poll_register(sor, PWM_CTL, 267 PWM_CTL_SETTING_NEW_SHIFT, 268 PWM_CTL_SETTING_NEW_DONE, 269 100, TEGRA_SOR_TIMEOUT_MS)) { 270 debug("dp: timeout while waiting for SOR PWM setting\n"); 271 } 272 } 273 274 static void tegra_dc_sor_set_dp_mode(struct udevice *dev, 275 const struct tegra_dp_link_config *link_cfg) 276 { 277 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 278 u32 reg_val; 279 280 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); 281 282 tegra_dc_sor_set_dp_linkctl(dev, 1, training_pattern_none, link_cfg); 283 reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum)); 284 reg_val &= ~DP_CONFIG_WATERMARK_MASK; 285 reg_val |= link_cfg->watermark; 286 reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK; 287 reg_val |= (link_cfg->active_count << 288 DP_CONFIG_ACTIVESYM_COUNT_SHIFT); 289 reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK; 290 reg_val |= (link_cfg->active_frac << 291 DP_CONFIG_ACTIVESYM_FRAC_SHIFT); 292 if (link_cfg->activepolarity) 293 reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; 294 else 295 reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE; 296 reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE | 297 DP_CONFIG_RD_RESET_VAL_NEGATIVE); 298 299 tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val); 300 301 /* program h/vblank sym */ 302 tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS, 303 DP_AUDIO_HBLANK_SYMBOLS_MASK, 304 link_cfg->hblank_sym); 305 306 tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS, 307 DP_AUDIO_VBLANK_SYMBOLS_MASK, 308 link_cfg->vblank_sym); 309 } 310 311 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor) 312 { 313 tegra_sor_writel(sor, SUPER_STATE0, 0); 314 tegra_sor_writel(sor, SUPER_STATE0, 1); 315 tegra_sor_writel(sor, SUPER_STATE0, 0); 316 } 317 318 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor) 319 { 320 tegra_sor_writel(sor, STATE0, 0); 321 tegra_sor_writel(sor, STATE0, 1); 322 tegra_sor_writel(sor, STATE0, 0); 323 } 324 325 static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up) 326 { 327 u32 reg_val; 328 void *pmc_base = sor->pmc_base; 329 330 if (up) { 331 writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE, 332 pmc_base + APBDEV_PMC_DPD_SAMPLE); 333 writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM); 334 } 335 336 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ); 337 reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON || 338 APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK); 339 340 reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON | 341 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF : 342 APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF | 343 APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON; 344 345 writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ); 346 347 /* Polling */ 348 u32 temp = 10 * 1000; 349 do { 350 udelay(20); 351 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS); 352 if (temp > 20) 353 temp -= 20; 354 else 355 break; 356 } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0); 357 358 if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) { 359 debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val); 360 return -EIO; 361 } 362 363 if (up) { 364 writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE, 365 pmc_base + APBDEV_PMC_DPD_SAMPLE); 366 } 367 368 return 0; 369 } 370 371 void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int) 372 { 373 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 374 u32 reg_val; 375 376 reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); 377 if (is_int) 378 reg_val |= DP_SPARE_PANEL_INTERNAL; 379 else 380 reg_val &= ~DP_SPARE_PANEL_INTERNAL; 381 382 reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK | 383 DP_SPARE_SEQ_ENABLE_YES; 384 tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val); 385 } 386 387 void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw, 388 u8 *lane_count) 389 { 390 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 391 u32 reg_val; 392 393 reg_val = tegra_sor_readl(sor, CLK_CNTRL); 394 *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK) 395 >> CLK_CNTRL_DP_LINK_SPEED_SHIFT; 396 reg_val = tegra_sor_readl(sor, 397 DP_LINKCTL(sor->portnum)); 398 399 switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) { 400 case DP_LINKCTL_LANECOUNT_ZERO: 401 *lane_count = 0; 402 break; 403 case DP_LINKCTL_LANECOUNT_ONE: 404 *lane_count = 1; 405 break; 406 case DP_LINKCTL_LANECOUNT_TWO: 407 *lane_count = 2; 408 break; 409 case DP_LINKCTL_LANECOUNT_FOUR: 410 *lane_count = 4; 411 break; 412 default: 413 printf("Unknown lane count\n"); 414 } 415 } 416 417 void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw) 418 { 419 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 420 421 tegra_sor_write_field(sor, CLK_CNTRL, 422 CLK_CNTRL_DP_LINK_SPEED_MASK, 423 link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT); 424 } 425 426 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) 427 { 428 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 429 u32 reg_val; 430 431 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); 432 reg_val &= ~DP_LINKCTL_LANECOUNT_MASK; 433 switch (lane_count) { 434 case 0: 435 break; 436 case 1: 437 reg_val |= DP_LINKCTL_LANECOUNT_ONE; 438 break; 439 case 2: 440 reg_val |= DP_LINKCTL_LANECOUNT_TWO; 441 break; 442 case 4: 443 reg_val |= DP_LINKCTL_LANECOUNT_FOUR; 444 break; 445 default: 446 /* 0 should be handled earlier. */ 447 printf("dp: Invalid lane count %d\n", lane_count); 448 return; 449 } 450 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); 451 } 452 453 /* 454 * The SOR power sequencer does not work for t124 so SW has to 455 * go through the power sequence manually 456 * Power up steps from spec: 457 * STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL 458 * 1 1 1 1 1 1 1 1 459 * 2 1 1 1 1 1 0 1 460 * 3 1 1 0 1 1 0 1 461 * 4 1 0 0 0 0 0 1 462 * 5 0 0 0 0 0 0 1 463 */ 464 static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds) 465 { 466 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 467 u32 reg; 468 int ret; 469 470 if (sor->power_is_up) 471 return 0; 472 473 /* 474 * If for some reason it is already powered up, don't do it again. 475 * This can happen if U-Boot is the secondary boot loader. 476 */ 477 reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); 478 if (reg & DP_PADCTL_PD_TXD_0_NO) 479 return 0; 480 481 /* Set link bw */ 482 tegra_dc_sor_set_link_bandwidth(dev, is_lvds ? 483 CLK_CNTRL_DP_LINK_SPEED_LVDS : 484 CLK_CNTRL_DP_LINK_SPEED_G1_62); 485 486 /* step 1 */ 487 tegra_sor_write_field(sor, PLL2, 488 PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */ 489 PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */ 490 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */ 491 PLL2_AUX7_PORT_POWERDOWN_ENABLE | 492 PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE | 493 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE); 494 tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */ 495 PLL0_VCOPD_MASK, /* PLLVCOPD */ 496 PLL0_PWR_OFF | PLL0_VCOPD_ASSERT); 497 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 498 DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */ 499 DP_PADCTL_PAD_CAL_PD_POWERDOWN); 500 501 /* step 2 */ 502 ret = tegra_dc_sor_io_set_dpd(sor, 1); 503 if (ret) 504 return ret; 505 udelay(15); 506 507 /* step 3 */ 508 tegra_sor_write_field(sor, PLL2, 509 PLL2_AUX6_BANDGAP_POWERDOWN_MASK, 510 PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); 511 udelay(25); 512 513 /* step 4 */ 514 tegra_sor_write_field(sor, PLL0, 515 PLL0_PWR_MASK | /* PDPLL */ 516 PLL0_VCOPD_MASK, /* PLLVCOPD */ 517 PLL0_PWR_ON | PLL0_VCOPD_RESCIND); 518 /* PLLCAPD */ 519 tegra_sor_write_field(sor, PLL2, 520 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, 521 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); 522 udelay(225); 523 524 /* step 5 PDPORT */ 525 tegra_sor_write_field(sor, PLL2, 526 PLL2_AUX7_PORT_POWERDOWN_MASK, 527 PLL2_AUX7_PORT_POWERDOWN_DISABLE); 528 529 sor->power_is_up = 1; 530 531 return 0; 532 } 533 534 #if DEBUG_SOR 535 static void dump_sor_reg(struct tegra_dc_sor_data *sor) 536 { 537 #define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \ 538 #a, a, tegra_sor_readl(sor, a)); 539 540 DUMP_REG(SUPER_STATE0); 541 DUMP_REG(SUPER_STATE1); 542 DUMP_REG(STATE0); 543 DUMP_REG(STATE1); 544 DUMP_REG(NV_HEAD_STATE0(0)); 545 DUMP_REG(NV_HEAD_STATE0(1)); 546 DUMP_REG(NV_HEAD_STATE1(0)); 547 DUMP_REG(NV_HEAD_STATE1(1)); 548 DUMP_REG(NV_HEAD_STATE2(0)); 549 DUMP_REG(NV_HEAD_STATE2(1)); 550 DUMP_REG(NV_HEAD_STATE3(0)); 551 DUMP_REG(NV_HEAD_STATE3(1)); 552 DUMP_REG(NV_HEAD_STATE4(0)); 553 DUMP_REG(NV_HEAD_STATE4(1)); 554 DUMP_REG(NV_HEAD_STATE5(0)); 555 DUMP_REG(NV_HEAD_STATE5(1)); 556 DUMP_REG(CRC_CNTRL); 557 DUMP_REG(CLK_CNTRL); 558 DUMP_REG(CAP); 559 DUMP_REG(PWR); 560 DUMP_REG(TEST); 561 DUMP_REG(PLL0); 562 DUMP_REG(PLL1); 563 DUMP_REG(PLL2); 564 DUMP_REG(PLL3); 565 DUMP_REG(CSTM); 566 DUMP_REG(LVDS); 567 DUMP_REG(CRCA); 568 DUMP_REG(CRCB); 569 DUMP_REG(SEQ_CTL); 570 DUMP_REG(LANE_SEQ_CTL); 571 DUMP_REG(SEQ_INST(0)); 572 DUMP_REG(SEQ_INST(1)); 573 DUMP_REG(SEQ_INST(2)); 574 DUMP_REG(SEQ_INST(3)); 575 DUMP_REG(SEQ_INST(4)); 576 DUMP_REG(SEQ_INST(5)); 577 DUMP_REG(SEQ_INST(6)); 578 DUMP_REG(SEQ_INST(7)); 579 DUMP_REG(SEQ_INST(8)); 580 DUMP_REG(PWM_DIV); 581 DUMP_REG(PWM_CTL); 582 DUMP_REG(MSCHECK); 583 DUMP_REG(XBAR_CTRL); 584 DUMP_REG(DP_LINKCTL(0)); 585 DUMP_REG(DP_LINKCTL(1)); 586 DUMP_REG(DC(0)); 587 DUMP_REG(DC(1)); 588 DUMP_REG(LANE_DRIVE_CURRENT(0)); 589 DUMP_REG(PR(0)); 590 DUMP_REG(LANE4_PREEMPHASIS(0)); 591 DUMP_REG(POSTCURSOR(0)); 592 DUMP_REG(DP_CONFIG(0)); 593 DUMP_REG(DP_CONFIG(1)); 594 DUMP_REG(DP_MN(0)); 595 DUMP_REG(DP_MN(1)); 596 DUMP_REG(DP_PADCTL(0)); 597 DUMP_REG(DP_PADCTL(1)); 598 DUMP_REG(DP_DEBUG(0)); 599 DUMP_REG(DP_DEBUG(1)); 600 DUMP_REG(DP_SPARE(0)); 601 DUMP_REG(DP_SPARE(1)); 602 DUMP_REG(DP_TPG); 603 604 return; 605 } 606 #endif 607 608 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, 609 int is_lvds, 610 const struct tegra_dp_link_config *link_cfg, 611 const struct display_timing *timing) 612 { 613 const int head_num = 0; 614 u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num; 615 u32 vtotal, htotal; 616 u32 vsync_end, hsync_end; 617 u32 vblank_end, hblank_end; 618 u32 vblank_start, hblank_start; 619 620 reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM : 621 STATE1_ASY_PROTOCOL_DP_A; 622 reg_val |= STATE1_ASY_SUBOWNER_NONE | 623 STATE1_ASY_CRCMODE_COMPLETE_RASTER; 624 625 reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE; 626 reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE; 627 reg_val |= (link_cfg->bits_per_pixel > 18) ? 628 STATE1_ASY_PIXELDEPTH_BPP_24_444 : 629 STATE1_ASY_PIXELDEPTH_BPP_18_444; 630 631 tegra_sor_writel(sor, STATE1, reg_val); 632 633 /* 634 * Skipping programming NV_HEAD_STATE0, assuming: 635 * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB 636 */ 637 vtotal = timing->vsync_len.typ + timing->vback_porch.typ + 638 timing->vactive.typ + timing->vfront_porch.typ; 639 htotal = timing->hsync_len.typ + timing->hback_porch.typ + 640 timing->hactive.typ + timing->hfront_porch.typ; 641 642 tegra_sor_writel(sor, NV_HEAD_STATE1(head_num), 643 vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT | 644 htotal << NV_HEAD_STATE1_HTOTAL_SHIFT); 645 646 vsync_end = timing->vsync_len.typ - 1; 647 hsync_end = timing->hsync_len.typ - 1; 648 tegra_sor_writel(sor, NV_HEAD_STATE2(head_num), 649 vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT | 650 hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT); 651 652 vblank_end = vsync_end + timing->vback_porch.typ; 653 hblank_end = hsync_end + timing->hback_porch.typ; 654 tegra_sor_writel(sor, NV_HEAD_STATE3(head_num), 655 vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT | 656 hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT); 657 658 vblank_start = vblank_end + timing->vactive.typ; 659 hblank_start = hblank_end + timing->hactive.typ; 660 tegra_sor_writel(sor, NV_HEAD_STATE4(head_num), 661 vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT | 662 hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT); 663 664 /* TODO: adding interlace mode support */ 665 tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1); 666 667 tegra_sor_write_field(sor, CSTM, 668 CSTM_ROTCLK_DEFAULT_MASK | 669 CSTM_LVDS_EN_ENABLE, 670 2 << CSTM_ROTCLK_SHIFT | 671 is_lvds ? CSTM_LVDS_EN_ENABLE : 672 CSTM_LVDS_EN_DISABLE); 673 674 tegra_dc_sor_config_pwm(sor, 1024, 1024); 675 } 676 677 static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl) 678 { 679 u32 reg_val = readl(&disp_ctrl->cmd.state_access); 680 681 writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); 682 writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt); 683 684 /* Enable DC now - otherwise pure text console may not show. */ 685 writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, 686 &disp_ctrl->cmd.disp_cmd); 687 writel(reg_val, &disp_ctrl->cmd.state_access); 688 } 689 690 int tegra_dc_sor_enable_dp(struct udevice *dev, 691 const struct tegra_dp_link_config *link_cfg) 692 { 693 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 694 int ret; 695 696 tegra_sor_write_field(sor, CLK_CNTRL, 697 CLK_CNTRL_DP_CLK_SEL_MASK, 698 CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK); 699 700 tegra_sor_write_field(sor, PLL2, 701 PLL2_AUX6_BANDGAP_POWERDOWN_MASK, 702 PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE); 703 udelay(25); 704 705 tegra_sor_write_field(sor, PLL3, 706 PLL3_PLLVDD_MODE_MASK, 707 PLL3_PLLVDD_MODE_V3_3); 708 tegra_sor_writel(sor, PLL0, 709 0xf << PLL0_ICHPMP_SHFIT | 710 0x3 << PLL0_VCOCAP_SHIFT | 711 PLL0_PLLREG_LEVEL_V45 | 712 PLL0_RESISTORSEL_EXT | 713 PLL0_PWR_ON | PLL0_VCOPD_RESCIND); 714 tegra_sor_write_field(sor, PLL2, 715 PLL2_AUX1_SEQ_MASK | 716 PLL2_AUX9_LVDSEN_OVERRIDE | 717 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, 718 PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE | 719 PLL2_AUX9_LVDSEN_OVERRIDE | 720 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE); 721 tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH | 722 PLL1_TMDS_TERM_ENABLE); 723 724 if (tegra_dc_sor_poll_register(sor, PLL2, 725 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, 726 PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE, 727 100, TEGRA_SOR_TIMEOUT_MS)) { 728 printf("DP failed to lock PLL\n"); 729 return -EIO; 730 } 731 732 tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK | 733 PLL2_AUX7_PORT_POWERDOWN_MASK, 734 PLL2_AUX2_OVERRIDE_POWERDOWN | 735 PLL2_AUX7_PORT_POWERDOWN_DISABLE); 736 737 ret = tegra_dc_sor_power_up(dev, 0); 738 if (ret) { 739 debug("DP failed to power up\n"); 740 return ret; 741 } 742 743 /* re-enable SOR clock */ 744 clock_sor_enable_edp_clock(); 745 746 /* Power up lanes */ 747 tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1); 748 749 tegra_dc_sor_set_dp_mode(dev, link_cfg); 750 debug("%s ret\n", __func__); 751 752 return 0; 753 } 754 755 int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev, 756 const struct tegra_dp_link_config *link_cfg, 757 const struct display_timing *timing) 758 { 759 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 760 struct dc_ctlr *disp_ctrl; 761 u32 reg_val; 762 763 /* Use the first display controller */ 764 debug("%s\n", __func__); 765 disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev); 766 767 tegra_dc_sor_enable_dc(disp_ctrl); 768 tegra_dc_sor_config_panel(sor, 0, link_cfg, timing); 769 770 writel(0x9f00, &disp_ctrl->cmd.state_ctrl); 771 writel(0x9f, &disp_ctrl->cmd.state_ctrl); 772 773 writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 774 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, 775 &disp_ctrl->cmd.disp_pow_ctrl); 776 777 reg_val = tegra_sor_readl(sor, TEST); 778 if (reg_val & TEST_ATTACHED_TRUE) 779 return -EEXIST; 780 781 tegra_sor_writel(sor, SUPER_STATE1, 782 SUPER_STATE1_ATTACHED_NO); 783 784 /* 785 * Enable display2sor clock at least 2 cycles before DC start, 786 * to clear sor internal valid signal. 787 */ 788 writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); 789 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); 790 writel(0, &disp_ctrl->disp.disp_win_opt); 791 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); 792 793 /* Attach head */ 794 tegra_dc_sor_update(sor); 795 tegra_sor_writel(sor, SUPER_STATE1, 796 SUPER_STATE1_ATTACHED_YES); 797 tegra_sor_writel(sor, SUPER_STATE1, 798 SUPER_STATE1_ATTACHED_YES | 799 SUPER_STATE1_ASY_HEAD_OP_AWAKE | 800 SUPER_STATE1_ASY_ORMODE_NORMAL); 801 tegra_dc_sor_super_update(sor); 802 803 /* Enable dc */ 804 reg_val = readl(&disp_ctrl->cmd.state_access); 805 writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); 806 writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, 807 &disp_ctrl->cmd.disp_cmd); 808 writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt); 809 writel(reg_val, &disp_ctrl->cmd.state_access); 810 811 if (tegra_dc_sor_poll_register(sor, TEST, 812 TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, 813 TEST_ACT_HEAD_OPMODE_AWAKE, 814 100, 815 TEGRA_SOR_ATTACH_TIMEOUT_MS)) { 816 printf("dc timeout waiting for OPMOD = AWAKE\n"); 817 return -ETIMEDOUT; 818 } else { 819 debug("%s: sor is attached\n", __func__); 820 } 821 822 #if DEBUG_SOR 823 dump_sor_reg(sor); 824 #endif 825 debug("%s: ret=%d\n", __func__, 0); 826 827 return 0; 828 } 829 830 void tegra_dc_sor_set_lane_parm(struct udevice *dev, 831 const struct tegra_dp_link_config *link_cfg) 832 { 833 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 834 835 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), 836 link_cfg->drive_current); 837 tegra_sor_writel(sor, PR(sor->portnum), 838 link_cfg->preemphasis); 839 tegra_sor_writel(sor, POSTCURSOR(sor->portnum), 840 link_cfg->postcursor); 841 tegra_sor_writel(sor, LVDS, 0); 842 843 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); 844 tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count); 845 846 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 847 DP_PADCTL_TX_PU_ENABLE | 848 DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, 849 DP_PADCTL_TX_PU_ENABLE | 850 2 << DP_PADCTL_TX_PU_VALUE_SHIFT); 851 852 /* Precharge */ 853 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); 854 udelay(20); 855 856 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); 857 } 858 859 int tegra_dc_sor_set_voltage_swing(struct udevice *dev, 860 const struct tegra_dp_link_config *link_cfg) 861 { 862 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 863 u32 drive_current = 0; 864 u32 pre_emphasis = 0; 865 866 /* Set to a known-good pre-calibrated setting */ 867 switch (link_cfg->link_bw) { 868 case SOR_LINK_SPEED_G1_62: 869 case SOR_LINK_SPEED_G2_7: 870 drive_current = 0x13131313; 871 pre_emphasis = 0; 872 break; 873 case SOR_LINK_SPEED_G5_4: 874 debug("T124 does not support 5.4G link clock.\n"); 875 default: 876 debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw); 877 return -ENOLINK; 878 } 879 880 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current); 881 tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis); 882 883 return 0; 884 } 885 886 void tegra_dc_sor_power_down_unused_lanes(struct udevice *dev, 887 const struct tegra_dp_link_config *link_cfg) 888 { 889 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 890 u32 pad_ctrl = 0; 891 int err = 0; 892 893 switch (link_cfg->lane_count) { 894 case 4: 895 pad_ctrl = DP_PADCTL_PD_TXD_0_NO | 896 DP_PADCTL_PD_TXD_1_NO | 897 DP_PADCTL_PD_TXD_2_NO | 898 DP_PADCTL_PD_TXD_3_NO; 899 break; 900 case 2: 901 pad_ctrl = DP_PADCTL_PD_TXD_0_NO | 902 DP_PADCTL_PD_TXD_1_NO | 903 DP_PADCTL_PD_TXD_2_YES | 904 DP_PADCTL_PD_TXD_3_YES; 905 break; 906 case 1: 907 pad_ctrl = DP_PADCTL_PD_TXD_0_NO | 908 DP_PADCTL_PD_TXD_1_YES | 909 DP_PADCTL_PD_TXD_2_YES | 910 DP_PADCTL_PD_TXD_3_YES; 911 break; 912 default: 913 printf("Invalid sor lane count: %u\n", link_cfg->lane_count); 914 return; 915 } 916 917 pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN; 918 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); 919 920 err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0); 921 if (err) { 922 debug("Wait for lane power down failed: %d\n", err); 923 return; 924 } 925 } 926 927 int tegra_sor_precharge_lanes(struct udevice *dev, 928 const struct tegra_dp_link_config *cfg) 929 { 930 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 931 u32 val = 0; 932 933 switch (cfg->lane_count) { 934 case 4: 935 val |= (DP_PADCTL_PD_TXD_3_NO | 936 DP_PADCTL_PD_TXD_2_NO); 937 /* fall through */ 938 case 2: 939 val |= DP_PADCTL_PD_TXD_1_NO; 940 /* fall through */ 941 case 1: 942 val |= DP_PADCTL_PD_TXD_0_NO; 943 break; 944 default: 945 debug("dp: invalid lane number %d\n", cfg->lane_count); 946 return -EINVAL; 947 } 948 949 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 950 (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 951 (val << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT)); 952 udelay(100); 953 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 954 (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT), 955 0); 956 957 return 0; 958 } 959 960 static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable) 961 { 962 u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt); 963 964 reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE; 965 writel(reg_val, &disp_ctrl->disp.disp_win_opt); 966 } 967 968 int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev) 969 { 970 struct tegra_dc_sor_data *sor = dev_get_priv(dev); 971 int dc_reg_ctx[DC_REG_SAVE_SPACE]; 972 struct dc_ctlr *disp_ctrl; 973 unsigned long dc_int_mask; 974 int ret; 975 976 debug("%s\n", __func__); 977 /* Use the first display controller */ 978 disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev); 979 980 /* Sleep mode */ 981 tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | 982 SUPER_STATE1_ASY_ORMODE_SAFE | 983 SUPER_STATE1_ATTACHED_YES); 984 tegra_dc_sor_super_update(sor); 985 986 tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx); 987 988 if (tegra_dc_sor_poll_register(sor, TEST, 989 TEST_ACT_HEAD_OPMODE_DEFAULT_MASK, 990 TEST_ACT_HEAD_OPMODE_SLEEP, 100, 991 TEGRA_SOR_ATTACH_TIMEOUT_MS)) { 992 debug("dc timeout waiting for OPMOD = SLEEP\n"); 993 ret = -ETIMEDOUT; 994 goto err; 995 } 996 997 tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP | 998 SUPER_STATE1_ASY_ORMODE_SAFE | 999 SUPER_STATE1_ATTACHED_NO); 1000 1001 /* Mask DC interrupts during the 2 dummy frames required for detach */ 1002 dc_int_mask = readl(&disp_ctrl->cmd.int_mask); 1003 writel(0, &disp_ctrl->cmd.int_mask); 1004 1005 /* Stop DC->SOR path */ 1006 tegra_dc_sor_enable_sor(disp_ctrl, false); 1007 ret = tegra_dc_sor_general_act(disp_ctrl); 1008 if (ret) 1009 goto err; 1010 1011 /* Stop DC */ 1012 writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd); 1013 ret = tegra_dc_sor_general_act(disp_ctrl); 1014 if (ret) 1015 goto err; 1016 1017 tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx); 1018 1019 writel(dc_int_mask, &disp_ctrl->cmd.int_mask); 1020 1021 return 0; 1022 err: 1023 debug("%s: ret=%d\n", __func__, ret); 1024 1025 return ret; 1026 } 1027 1028 static int tegra_sor_set_backlight(struct udevice *dev, int percent) 1029 { 1030 struct tegra_dc_sor_data *priv = dev_get_priv(dev); 1031 int ret; 1032 1033 ret = panel_enable_backlight(priv->panel); 1034 if (ret) { 1035 debug("sor: Cannot enable panel backlight\n"); 1036 return ret; 1037 } 1038 1039 return 0; 1040 } 1041 1042 static int tegra_sor_ofdata_to_platdata(struct udevice *dev) 1043 { 1044 struct tegra_dc_sor_data *priv = dev_get_priv(dev); 1045 int ret; 1046 1047 priv->base = (void *)dev_read_addr(dev); 1048 1049 priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC); 1050 if (IS_ERR(priv->pmc_base)) 1051 return PTR_ERR(priv->pmc_base); 1052 1053 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel", 1054 &priv->panel); 1055 if (ret) { 1056 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__, 1057 dev->name, ret); 1058 return ret; 1059 } 1060 1061 return 0; 1062 } 1063 1064 static const struct video_bridge_ops tegra_sor_ops = { 1065 .set_backlight = tegra_sor_set_backlight, 1066 }; 1067 1068 static const struct udevice_id tegra_sor_ids[] = { 1069 { .compatible = "nvidia,tegra124-sor" }, 1070 { } 1071 }; 1072 1073 U_BOOT_DRIVER(sor_tegra) = { 1074 .name = "sor_tegra", 1075 .id = UCLASS_VIDEO_BRIDGE, 1076 .of_match = tegra_sor_ids, 1077 .ofdata_to_platdata = tegra_sor_ofdata_to_platdata, 1078 .ops = &tegra_sor_ops, 1079 .priv_auto_alloc_size = sizeof(struct tegra_dc_sor_data), 1080 }; 1081