1 /* 2 * Copyright 2014 Google Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Extracted from Chromium coreboot commit 3f59b13d 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <edid.h> 12 #include <errno.h> 13 #include <display.h> 14 #include <edid.h> 15 #include <lcd.h> 16 #include <video.h> 17 #include <asm/gpio.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/pwm.h> 21 #include <asm/arch-tegra/dc.h> 22 #include <dm/uclass-internal.h> 23 #include "displayport.h" 24 25 /* return in 1000ths of a Hertz */ 26 static int tegra_dc_calc_refresh(const struct display_timing *timing) 27 { 28 int h_total, v_total, refresh; 29 int pclk = timing->pixelclock.typ; 30 31 h_total = timing->hactive.typ + timing->hfront_porch.typ + 32 timing->hback_porch.typ + timing->hsync_len.typ; 33 v_total = timing->vactive.typ + timing->vfront_porch.typ + 34 timing->vback_porch.typ + timing->vsync_len.typ; 35 if (!pclk || !h_total || !v_total) 36 return 0; 37 refresh = pclk / h_total; 38 refresh *= 1000; 39 refresh /= v_total; 40 41 return refresh; 42 } 43 44 static void print_mode(const struct display_timing *timing) 45 { 46 int refresh = tegra_dc_calc_refresh(timing); 47 48 debug("MODE:%dx%d@%d.%03uHz pclk=%d\n", 49 timing->hactive.typ, timing->vactive.typ, refresh / 1000, 50 refresh % 1000, timing->pixelclock.typ); 51 } 52 53 static int update_display_mode(struct dc_ctlr *disp_ctrl, 54 const struct display_timing *timing, 55 int href_to_sync, int vref_to_sync) 56 { 57 print_mode(timing); 58 59 writel(0x1, &disp_ctrl->disp.disp_timing_opt); 60 61 writel(vref_to_sync << 16 | href_to_sync, 62 &disp_ctrl->disp.ref_to_sync); 63 64 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, 65 &disp_ctrl->disp.sync_width); 66 67 writel(((timing->vback_porch.typ - vref_to_sync) << 16) | 68 timing->hback_porch.typ, &disp_ctrl->disp.back_porch); 69 70 writel(((timing->vfront_porch.typ + vref_to_sync) << 16) | 71 timing->hfront_porch.typ, &disp_ctrl->disp.front_porch); 72 73 writel(timing->hactive.typ | (timing->vactive.typ << 16), 74 &disp_ctrl->disp.disp_active); 75 76 /** 77 * We want to use PLLD_out0, which is PLLD / 2: 78 * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv. 79 * 80 * Currently most panels work inside clock range 50MHz~100MHz, and PLLD 81 * has some requirements to have VCO in range 500MHz~1000MHz (see 82 * clock.c for more detail). To simplify calculation, we set 83 * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values 84 * may be calculated by clock_display, to allow wider frequency range. 85 * 86 * Note ShiftClockDiv is a 7.1 format value. 87 */ 88 const u32 shift_clock_div = 1; 89 writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | 90 ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT, 91 &disp_ctrl->disp.disp_clk_ctrl); 92 debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__, 93 timing->pixelclock.typ, shift_clock_div); 94 return 0; 95 } 96 97 static u32 tegra_dc_poll_register(void *reg, 98 u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us) 99 { 100 u32 temp = timeout_us; 101 u32 reg_val = 0; 102 103 do { 104 udelay(poll_interval_us); 105 reg_val = readl(reg); 106 if (timeout_us > poll_interval_us) 107 timeout_us -= poll_interval_us; 108 else 109 break; 110 } while ((reg_val & mask) != exp_val); 111 112 if ((reg_val & mask) == exp_val) 113 return 0; /* success */ 114 115 return temp; 116 } 117 118 int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl) 119 { 120 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); 121 122 if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl, 123 GENERAL_ACT_REQ, 0, 100, 124 DC_POLL_TIMEOUT_MS * 1000)) { 125 debug("dc timeout waiting for DC to stop\n"); 126 return -ETIMEDOUT; 127 } 128 129 return 0; 130 } 131 132 static struct display_timing min_mode = { 133 .hsync_len = { .typ = 1 }, 134 .vsync_len = { .typ = 1 }, 135 .hback_porch = { .typ = 20 }, 136 .vback_porch = { .typ = 0 }, 137 .hactive = { .typ = 16 }, 138 .vactive = { .typ = 16 }, 139 .hfront_porch = { .typ = 1 }, 140 .vfront_porch = { .typ = 2 }, 141 }; 142 143 /* Disable windows and set minimum raster timings */ 144 void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, 145 int *dc_reg_ctx) 146 { 147 const int href_to_sync = 0, vref_to_sync = 1; 148 int selected_windows, i; 149 150 selected_windows = readl(&disp_ctrl->cmd.disp_win_header); 151 152 /* Store and clear window options */ 153 for (i = 0; i < DC_N_WINDOWS; ++i) { 154 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); 155 dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt); 156 writel(0, &disp_ctrl->win.win_opt); 157 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); 158 } 159 160 writel(selected_windows, &disp_ctrl->cmd.disp_win_header); 161 162 /* Store current raster timings and set minimum timings */ 163 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync); 164 writel(href_to_sync | (vref_to_sync << 16), 165 &disp_ctrl->disp.ref_to_sync); 166 167 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width); 168 writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16), 169 &disp_ctrl->disp.sync_width); 170 171 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch); 172 writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16), 173 &disp_ctrl->disp.back_porch); 174 175 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch); 176 writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16), 177 &disp_ctrl->disp.front_porch); 178 179 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active); 180 writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16), 181 &disp_ctrl->disp.disp_active); 182 183 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); 184 } 185 186 /* Restore previous windows status and raster timings */ 187 void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, 188 int *dc_reg_ctx) 189 { 190 int selected_windows, i; 191 192 selected_windows = readl(&disp_ctrl->cmd.disp_win_header); 193 194 for (i = 0; i < DC_N_WINDOWS; ++i) { 195 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); 196 writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt); 197 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); 198 } 199 200 writel(selected_windows, &disp_ctrl->cmd.disp_win_header); 201 202 writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync); 203 writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width); 204 writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch); 205 writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch); 206 writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active); 207 208 writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl); 209 } 210 211 static int tegra_depth_for_bpp(int bpp) 212 { 213 switch (bpp) { 214 case 32: 215 return COLOR_DEPTH_R8G8B8A8; 216 case 16: 217 return COLOR_DEPTH_B5G6R5; 218 default: 219 debug("Unsupported LCD bit depth"); 220 return -1; 221 } 222 } 223 224 static int update_window(struct dc_ctlr *disp_ctrl, 225 u32 frame_buffer, int fb_bits_per_pixel, 226 const struct display_timing *timing) 227 { 228 const u32 colour_white = 0xffffff; 229 int colour_depth; 230 u32 val; 231 232 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); 233 234 writel(((timing->vactive.typ << 16) | timing->hactive.typ), 235 &disp_ctrl->win.size); 236 writel(((timing->vactive.typ << 16) | 237 (timing->hactive.typ * fb_bits_per_pixel / 8)), 238 &disp_ctrl->win.prescaled_size); 239 writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) / 240 32 * 32), &disp_ctrl->win.line_stride); 241 242 colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel); 243 if (colour_depth == -1) 244 return -EINVAL; 245 246 writel(colour_depth, &disp_ctrl->win.color_depth); 247 248 writel(frame_buffer, &disp_ctrl->winbuf.start_addr); 249 writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT, 250 &disp_ctrl->win.dda_increment); 251 252 writel(colour_white, &disp_ctrl->disp.blend_background_color); 253 writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, 254 &disp_ctrl->cmd.disp_cmd); 255 256 writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); 257 258 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; 259 val |= GENERAL_UPDATE | WIN_A_UPDATE; 260 writel(val, &disp_ctrl->cmd.state_ctrl); 261 262 /* Enable win_a */ 263 val = readl(&disp_ctrl->win.win_opt); 264 writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt); 265 266 return 0; 267 } 268 269 static int tegra_dc_init(struct dc_ctlr *disp_ctrl) 270 { 271 /* do not accept interrupts during initialization */ 272 writel(0x00000000, &disp_ctrl->cmd.int_mask); 273 writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, 274 &disp_ctrl->cmd.state_access); 275 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); 276 writel(0x00000000, &disp_ctrl->win.win_opt); 277 writel(0x00000000, &disp_ctrl->win.byte_swap); 278 writel(0x00000000, &disp_ctrl->win.buffer_ctrl); 279 280 writel(0x00000000, &disp_ctrl->win.pos); 281 writel(0x00000000, &disp_ctrl->win.h_initial_dda); 282 writel(0x00000000, &disp_ctrl->win.v_initial_dda); 283 writel(0x00000000, &disp_ctrl->win.dda_increment); 284 writel(0x00000000, &disp_ctrl->win.dv_ctrl); 285 286 writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl); 287 writel(0x00000000, &disp_ctrl->win.blend_match_select); 288 writel(0x00000000, &disp_ctrl->win.blend_nomatch_select); 289 writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit); 290 291 writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi); 292 writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset); 293 writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset); 294 295 writel(0x00000000, &disp_ctrl->com.crc_checksum); 296 writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]); 297 writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]); 298 writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]); 299 writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]); 300 writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0); 301 302 return 0; 303 } 304 305 static void dump_config(int panel_bpp, struct display_timing *timing) 306 { 307 printf("timing->hactive.typ = %d\n", timing->hactive.typ); 308 printf("timing->vactive.typ = %d\n", timing->vactive.typ); 309 printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); 310 311 printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ); 312 printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ); 313 printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ); 314 315 printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ); 316 printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ); 317 printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ); 318 319 printf("panel_bits_per_pixel = %d\n", panel_bpp); 320 } 321 322 static int display_update_config_from_edid(struct udevice *dp_dev, 323 int *panel_bppp, 324 struct display_timing *timing) 325 { 326 return display_read_timing(dp_dev, timing); 327 } 328 329 static int display_init(struct udevice *dev, void *lcdbase, 330 int fb_bits_per_pixel, struct display_timing *timing) 331 { 332 struct display_plat *disp_uc_plat; 333 struct dc_ctlr *dc_ctlr; 334 struct udevice *dp_dev; 335 const int href_to_sync = 1, vref_to_sync = 1; 336 int panel_bpp = 18; /* default 18 bits per pixel */ 337 u32 plld_rate; 338 int ret; 339 340 /* 341 * Before we probe the display device (eDP), tell it that this device 342 * is the source of the display data. 343 */ 344 ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev); 345 if (ret) { 346 debug("%s: device '%s' display not found (ret=%d)\n", __func__, 347 dev->name, ret); 348 return ret; 349 } 350 351 disp_uc_plat = dev_get_uclass_platdata(dp_dev); 352 debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name, 353 disp_uc_plat); 354 disp_uc_plat->src_dev = dev; 355 356 ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev); 357 if (ret) { 358 debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret); 359 return ret; 360 } 361 362 dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev); 363 if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { 364 debug("%s: Failed to decode display timing\n", __func__); 365 return -EINVAL; 366 } 367 368 ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); 369 if (ret) { 370 debug("%s: Failed to decode EDID, using defaults\n", __func__); 371 dump_config(panel_bpp, timing); 372 } 373 374 /* 375 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER 376 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the 377 * update_display_mode() for detail. 378 */ 379 plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); 380 if (plld_rate == 0) { 381 printf("dc: clock init failed\n"); 382 return -EIO; 383 } else if (plld_rate != timing->pixelclock.typ * 2) { 384 debug("dc: plld rounded to %u\n", plld_rate); 385 timing->pixelclock.typ = plld_rate / 2; 386 } 387 388 /* Init dc */ 389 ret = tegra_dc_init(dc_ctlr); 390 if (ret) { 391 debug("dc: init failed\n"); 392 return ret; 393 } 394 395 /* Configure dc mode */ 396 ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); 397 if (ret) { 398 debug("dc: failed to configure display mode\n"); 399 return ret; 400 } 401 402 /* Enable dp */ 403 ret = display_enable(dp_dev, panel_bpp, timing); 404 if (ret) { 405 debug("dc: failed to enable display: ret=%d\n", ret); 406 return ret; 407 } 408 409 ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); 410 if (ret) { 411 debug("dc: failed to update window\n"); 412 return ret; 413 } 414 debug("%s: ready\n", __func__); 415 416 return 0; 417 } 418 419 enum { 420 /* Maximum LCD size we support */ 421 LCD_MAX_WIDTH = 1920, 422 LCD_MAX_HEIGHT = 1200, 423 LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ 424 }; 425 426 static int tegra124_lcd_init(struct udevice *dev, void *lcdbase, 427 enum video_log2_bpp l2bpp) 428 { 429 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 430 struct display_timing timing; 431 int ret; 432 433 clock_set_up_plldp(); 434 clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000); 435 436 clock_enable(PERIPH_ID_HOST1X); 437 clock_enable(PERIPH_ID_DISP1); 438 clock_enable(PERIPH_ID_PWM); 439 clock_enable(PERIPH_ID_DPAUX); 440 clock_enable(PERIPH_ID_SOR0); 441 udelay(2); 442 443 reset_set_enable(PERIPH_ID_HOST1X, 0); 444 reset_set_enable(PERIPH_ID_DISP1, 0); 445 reset_set_enable(PERIPH_ID_PWM, 0); 446 reset_set_enable(PERIPH_ID_DPAUX, 0); 447 reset_set_enable(PERIPH_ID_SOR0, 0); 448 449 ret = display_init(dev, lcdbase, 1 << l2bpp, &timing); 450 if (ret) 451 return ret; 452 453 uc_priv->xsize = roundup(timing.hactive.typ, 16); 454 uc_priv->ysize = timing.vactive.typ; 455 uc_priv->bpix = l2bpp; 456 457 video_set_flush_dcache(dev, 1); 458 debug("%s: done\n", __func__); 459 460 return 0; 461 } 462 463 static int tegra124_lcd_probe(struct udevice *dev) 464 { 465 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 466 ulong start; 467 int ret; 468 469 start = get_timer(0); 470 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd"); 471 ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16); 472 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); 473 debug("LCD init took %lu ms\n", get_timer(start)); 474 if (ret) 475 printf("%s: Error %d\n", __func__, ret); 476 477 return 0; 478 } 479 480 static int tegra124_lcd_bind(struct udevice *dev) 481 { 482 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); 483 484 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * 485 (1 << VIDEO_BPP16) / 8; 486 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); 487 488 return 0; 489 } 490 491 static const struct udevice_id tegra124_lcd_ids[] = { 492 { .compatible = "nvidia,tegra124-dc" }, 493 { } 494 }; 495 496 U_BOOT_DRIVER(tegra124_dc) = { 497 .name = "tegra124-dc", 498 .id = UCLASS_VIDEO, 499 .of_match = tegra124_lcd_ids, 500 .bind = tegra124_lcd_bind, 501 .probe = tegra124_lcd_probe, 502 }; 503