1 /* 2 * Copyright (c) 2016 Rockchip, Inc. 3 * Authors: Daniel Meng <daniel.meng@rock-chips.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <dm.h> 9 #include <fdtdec.h> 10 #include <libfdt.h> 11 #include <malloc.h> 12 #include <usb.h> 13 #include <watchdog.h> 14 #include <linux/errno.h> 15 #include <linux/compat.h> 16 #include <linux/usb/dwc3.h> 17 #include <power/regulator.h> 18 19 #include "xhci.h" 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 struct rockchip_xhci_platdata { 24 fdt_addr_t hcd_base; 25 fdt_addr_t phy_base; 26 struct udevice *vbus_supply; 27 }; 28 29 /* 30 * Contains pointers to register base addresses 31 * for the usb controller. 32 */ 33 struct rockchip_xhci { 34 struct usb_platdata usb_plat; 35 struct xhci_ctrl ctrl; 36 struct xhci_hccr *hcd; 37 struct dwc3 *dwc3_reg; 38 }; 39 40 static int xhci_usb_ofdata_to_platdata(struct udevice *dev) 41 { 42 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 43 struct udevice *child; 44 int ret = 0; 45 46 /* 47 * Get the base address for XHCI controller from the device node 48 */ 49 plat->hcd_base = devfdt_get_addr(dev); 50 if (plat->hcd_base == FDT_ADDR_T_NONE) { 51 debug("Can't get the XHCI register base address\n"); 52 return -ENXIO; 53 } 54 55 /* Get the base address for usbphy from the device node */ 56 for (device_find_first_child(dev, &child); child; 57 device_find_next_child(&child)) { 58 if (!device_is_compatible(child, "rockchip,rk3399-usb3-phy")) 59 continue; 60 plat->phy_base = devfdt_get_addr(child); 61 break; 62 } 63 64 if (plat->phy_base == FDT_ADDR_T_NONE) { 65 debug("Can't get the usbphy register address\n"); 66 return -ENXIO; 67 } 68 69 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) 70 /* Vbus regulator */ 71 ret = device_get_supply_regulator(dev, "vbus-supply", 72 &plat->vbus_supply); 73 if (ret) 74 debug("Can't get vbus supply\n"); 75 #endif 76 77 return 0; 78 } 79 80 /* 81 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core 82 * @dwc: Pointer to our controller context structure 83 * @dev: Pointer to ulcass device 84 */ 85 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, 86 struct udevice *dev) 87 { 88 u32 reg; 89 const void *blob = gd->fdt_blob; 90 u32 utmi_bits; 91 92 /* Set dwc3 usb2 phy config */ 93 reg = readl(&dwc3_reg->g_usb2phycfg[0]); 94 95 if (fdtdec_get_bool(blob, dev_of_offset(dev), 96 "snps,dis-enblslpm-quirk")) 97 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 98 99 utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev), 100 "snps,phyif-utmi-bits", -1); 101 if (utmi_bits == 16) { 102 reg |= DWC3_GUSB2PHYCFG_PHYIF; 103 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 104 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; 105 } else if (utmi_bits == 8) { 106 reg &= ~DWC3_GUSB2PHYCFG_PHYIF; 107 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; 108 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; 109 } 110 111 if (fdtdec_get_bool(blob, dev_of_offset(dev), 112 "snps,dis-u2-freeclk-exists-quirk")) 113 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 114 115 if (fdtdec_get_bool(blob, dev_of_offset(dev), 116 "snps,dis-u2-susphy-quirk")) 117 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 118 119 writel(reg, &dwc3_reg->g_usb2phycfg[0]); 120 } 121 122 static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, 123 struct udevice *dev) 124 { 125 int ret; 126 127 ret = dwc3_core_init(rkxhci->dwc3_reg); 128 if (ret) { 129 debug("failed to initialize core\n"); 130 return ret; 131 } 132 133 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); 134 135 /* We are hard-coding DWC3 core to Host Mode */ 136 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); 137 138 return 0; 139 } 140 141 static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) 142 { 143 return 0; 144 } 145 146 static int xhci_usb_probe(struct udevice *dev) 147 { 148 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 149 struct rockchip_xhci *ctx = dev_get_priv(dev); 150 struct xhci_hcor *hcor; 151 int ret; 152 153 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; 154 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); 155 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + 156 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); 157 158 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) 159 ret = regulator_set_enable(plat->vbus_supply, true); 160 if (ret) 161 debug("XHCI: Failed to enable vbus supply\n"); 162 #endif 163 164 ret = rockchip_xhci_core_init(ctx, dev); 165 if (ret) { 166 debug("XHCI: failed to initialize controller\n"); 167 return ret; 168 } 169 170 return xhci_register(dev, ctx->hcd, hcor); 171 } 172 173 static int xhci_usb_remove(struct udevice *dev) 174 { 175 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); 176 struct rockchip_xhci *ctx = dev_get_priv(dev); 177 int ret; 178 179 ret = xhci_deregister(dev); 180 if (ret) 181 return ret; 182 ret = rockchip_xhci_core_exit(ctx); 183 if (ret) 184 return ret; 185 186 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) 187 ret = regulator_set_enable(plat->vbus_supply, false); 188 if (ret) 189 debug("XHCI: Failed to disable vbus supply\n"); 190 #endif 191 192 return 0; 193 } 194 195 static const struct udevice_id xhci_usb_ids[] = { 196 { .compatible = "rockchip,rk3399-xhci" }, 197 { .compatible = "rockchip,rk3328-xhci" }, 198 { } 199 }; 200 201 U_BOOT_DRIVER(usb_xhci) = { 202 .name = "xhci_rockchip", 203 .id = UCLASS_USB, 204 .of_match = xhci_usb_ids, 205 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, 206 .probe = xhci_usb_probe, 207 .remove = xhci_usb_remove, 208 .ops = &xhci_usb_ops, 209 .bind = dm_scan_fdt_dev, 210 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), 211 .priv_auto_alloc_size = sizeof(struct rockchip_xhci), 212 .flags = DM_FLAG_ALLOC_PRIV_DMA, 213 }; 214 215 static const struct udevice_id usb_phy_ids[] = { 216 { .compatible = "rockchip,rk3399-usb3-phy" }, 217 { .compatible = "rockchip,rk3328-usb3-phy" }, 218 { } 219 }; 220 221 U_BOOT_DRIVER(usb_phy) = { 222 .name = "usb_phy_rockchip", 223 .of_match = usb_phy_ids, 224 }; 225